Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.

Abstract: A semiconductor structure includes a first semiconducting channel having a plurality of vertical nanowires and a second semiconducting channel having a plurality of vertical nanowires. The first semiconducting channel and the second semiconducting channel are configured to be in a stacked configuration. The plurality of vertical nanowires of the first semiconducting channel are configured to be in alternating positions relative to the plurality of vertical nanowires of the second semiconducting channel.

Abstract: An electronic device may include an optical image sensor that includes an array of optical image sensing pixels and a pin hole array mask layer above the optical image sensor and that includes spaced apart pin holes therein defining spaced apart image areas on the optical image sensor. The electronic device also includes a display layer above the pin hole array mask layer that includes spaced apart display pixels. The electronic device may also include processing circuitry coupled to the optical image sensor and capable of sensing images from spaced apart sub-arrays of the array of optical image sensing pixels aligned with the spaced apart image areas.

Abstract: Methods of forming thin-film structures including one or more NbMC layers, and structures and devices including the one or more NbMC layers are disclosed. The NbMC layers enable tuning of various structure and device properties, including resistivity, current leakage, and work function.

Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Abstract: According to an exemplary embodiment, a method of forming an isolation layer is provided. The method includes the following operations: providing a substrate; providing a vertical structure having a first layer over the substrate; providing a first interlayer dielectric over the first layer; performing CMP on the first interlayer dielectric; and etching back the first interlayer dielectric and the first layer to form the isolation layer corresponding to a source of the vertical structure.

Abstract: A display panel including an anode layer, a functional layer, a cathode layer, and a packaging layer is provided, in which the functional layer includes a hole transport layer, a light-emitting layer, a reflective layer, and an electron transport layer. The display panel has an advantage in increasing light transmittance.

Abstract: A highly reliable light-emitting device and a manufacturing method thereof are provided. A light-emitting element and a terminal electrode are formed over an element formation substrate; a first substrate having an opening is formed over the light-emitting element and the terminal electrode with a bonding layer provided therebetween; an embedded layer is formed in the opening; a transfer substrate is formed over the first substrate and the embedded layer; the element formation substrate is separated; a second substrate is formed under the light-emitting element and the terminal electrode; and the transfer substrate and the embedded layer are removed. In addition, an anisotropic conductive connection layer is formed in the opening, and an electrode is formed over the anisotropic conductive connection layer. The terminal electrode and the electrode are electrically connected to each other through the anisotropic conductive connection layer.

Abstract: A semiconductor device package includes a display device, an electronic module and a conductive adhesion layer. The display device includes a first substrate and a TFT layer. The first substrate has a first surface and a second surface opposite to the first surface. The TFT layer is disposed on the first surface of the first substrate. The electronic module includes a second substrate and an electronic component. The second substrate has a first surface facing the second surface of the first substrate and a second surface opposite to the first surface. The electronic component is disposed on the second surface of the second substrate. The conductive adhesion layer is disposed between the first substrate and the second substrate.

Abstract: A method may include providing a substrate, where the substrate includes a first main surface and a second main surface, opposite the first main surface. The second main surface may include a stress compensation layer. The method may include directing ions to the stress compensation layer in an ion implant procedure. The ion implant procedure may include exposing a first region of the stress compensation layer to a first implant process, wherein a second region of the stress compensation layer is not exposed to the first implant process.

Abstract: A shift control method in manufacture of semiconductor device includes at least the following step. An overlay offset of a first target of a semiconductor die and a second target of the semiconductor die is determined, where the second target is disposed on the first target. The semiconductor die is placed over a carrier, where placing the semiconductor die includes feeding back the overlay offset to result in a positional control of the semiconductor die. The semiconductor die is post processed to form a semiconductor device. Other shift control methods in manufacture of semiconductor device are also provided.

Abstract: A method is presented for forming a vertical transport field effect transistor (VTFET). The method includes forming a plurality of fins over a substrate, depositing a sacrificial material adjacent the plurality of fins, forming self-aligned spacers adjacent the plurality of fins, removing the sacrificial material to define openings under the self-aligned spacers, filling the openings with bottom spacers, depositing an interlayer dielectric (ILD) after patterning, laterally etching the substrate such that bottom surfaces of the plurality of fins are exposed, the lateral etching defining cavities within the substrate, and filling the cavities with an epitaxial material such that epitaxial regions are defined each having a symmetric tapered shape under a twin-fin structure. The single fin device can be formed through additional patterning and bottom epi under the single fin device that has an asymmetric tapered shape.

Abstract: A method of cleaving includes providing a substrate. Optionally, the substrate includes ?-gallium oxide, hexagonal zinc sulfide, or magnesium selenide. The substrate includes at least one natural cleave plane and a crystallinity. The substrate is cleaved along a first natural cleave plane of the at least one natural cleave plane. The cleaving the substrate along the first natural cleave plane includes the following. A micro-crack is generated in the substrate while maintaining the crystallinity adjacent to the micro-crack by generating a plurality of phonons in the substrate, the micro-crack comprising a micro-crack direction along the first natural cleave plane. The micro-crack is propagated along the first natural cleave plane while maintaining the crystallinity adjacent to the micro-crack. Optionally, generating a micro-crack in the substrate by generating a plurality of phonons in the substrate includes generating the plurality of phonons by electron-hole recombination.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate includes a first region and a second region. The semiconductor device structure includes a first conductive structure formed over the first region of the substrate and a bottom magnetic layer formed over the second region of the substrate. The semiconductor device structure also includes a second conductive structure formed over the bottom magnetic layer and a first insulating layer formed over a sidewall surface of the first conductive structure. The semiconductor device structure further includes a second insulating layer formed over the first insulating layer, and the second insulating layer has a stair-shaped structure.

Abstract: Improved top source and drain contact designs for VTFET devices are provided. In one aspect, a method of forming a VTFET device includes: depositing a first ILD over a VTFET structure having fins patterned in a substrate, bottom source and drains at a base of the fins, bottom spacers on the bottom source and drains and gates alongside the fins; patterning trenches in the first ILD; forming top spacers lining the trenches; forming top source and drains in the trenches at the tops of the fins; forming sacrificial caps covering the top source and drains; depositing a second ILD onto the first ILD; patterning contact trenches in the second ILD, exposing the sacrificial caps; removing the sacrificial caps through the contact trenches; and forming top source and drain contacts in the contact trenches that wrap around the top source and drains. A VTFET device is also provided.

Abstract: A method of manufacturing a semiconductor integrated circuit, includes: forming a first well region having a second conductivity type in an upper portion of a support layer having a first conductivity type; forming an oxide film on the first well region by a thermal oxidation method to decrease a concentration of impurities at an top surface of top surface side of the first well region; removing the oxide film; forming a second well region having the first conductivity type in an upper portion of the first well region; and merging a semiconductor element having a main electrode region having the second conductivity type in the second well region.

Abstract: An OLED display device includes a substrate, subpixel lines on the substrate and an applied-material separation layer on the substrate. Each of the subpixel lines includes subpixels of the same color disposed along a first axis. The applied-material separation layer has application separation openings. Each of the application separation openings includes subpixels of the same color that are consecutive in one subpixel line. Within each application separation opening, organic light-emitting films of the subpixels of the same color are connected by an organic light-emitting film made of the same material as material of the organic light-emitting films of the subpixels. Banks between application separation openings in each of the subpixel lines are different in position from banks between application separation openings in an adjacent subpixel line when seen along a second axis perpendicular to the first axis.

Abstract: The present disclosure describes one or more embodiment of a method for creating a patterned quantum dot layer. The method includes bringing a patterning stamp in contact with a layer of quantum dots disposed on a substrate, the patterning stamp comprising a patterned photoresist layer disposed on an elastomer layer, such that a portion of the quantum dots in contact with the patterned photoresist layer adheres to the patterning stamp, the portion of the quantum dots being adhered quantum dots. The method also includes peeling the patterning stamp from the substrate with a peeling speed larger than a pre-determined peeling speed to remove the adhered quantum dots from the substrate. A remaining portion of the quantum dots forms a patterned quantum dot layer on the substrate.

Abstract: Implementation of a device with stacked transistors comprising: a first transistor of a first type, in particular N or P, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other and aligned with each other, a second transistor of a second type, in particular P or N, with a gate-surrounding gate and a channel region formed in one or more second semi-conducting rods of said semi-conducting structure and disposed above the first semi-conducting rods, the source block of the second transistor being distinct from the source and drain block of the second transistor, the drain block of the second transistor being distinct from the drain and source blocks of the second transistor.

Abstract: A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure.