Abstract: A circuit which includes apparatus for determining for at each node of a multi-node interconnect the highest priority data present for transfer to that node, apparatus for storing information indicating the last node from which a transfer of data occurred at each priority level, apparatus for selecting for each priority level of data available at the node the last node from which a transfer of data occurred at each priority level, apparatus for weighting data at each priority level depending on the data last chosen at that level of priority, and means for selecting from all of the data available at each node the data having both the highest priority and having been chosen least recently at that priority levels of data at that node.

Abstract: An interrupt mechanism allows an interrupt request signal to be adjusted to any priority level specified by the user and provides to a CPU an encoded interrupt signal which either indicates that the interrupt priority has been adjusted or identifies a highest prioritized interrupt request when no adjustment in priority is made. A first logic circuit functions to receive a priority adjust request signal and compares the adjust signal with one or more interrupt signals to determine if an adjustment is required. A second logic circuit functions to identify the highest prioritized interrupt request of a plurality of interrupt requests and provides the encoded interrupt signal in response thereto. In one form, the encoded interrupt signal is translated into a value for use in a software exception processing routine within the CPU. The software exception processing routine can perform a variety of user specified functions with the encoded adjusted priority interrupt signal.

Abstract: In a multiprocessor computer system, wasted bus bandwidth resulting from slow responding slaves is reduced by relinquishing the master that was busied by the slow responding slave, and then causing the slave to effectively arbitrate for bus control on the relinquished master's behalf when the slow responding slave is either available to service the master or has the requested data. In accordance with the disclosed embodiment, the slave effectively arbitrates for bus control on the relinquished master's behalf by placing a unique arbitration code associated with the relinquished master on the bus. The relinquished master detects the presence of its arbitration code and then again arbitrates for bus control so that it may communicate with the slow responding slave.

Abstract: An intelligence information processing system is composed of an associative memory and a serial processing-type computer. Input pattern information is associated with the associative memory, and pattern recognition based on the computer evaluates an associative output. In accordance with this evaluation, an associative and restrictive condition is repeatedly added to the energy function of a neural network constituting the associative memory, thereby converging the associative output on a stable state of the energy. The converged associative output is verified with intelligence information stored in a computer memory. The associative and restrictive condition is again repeatedly added to the energy function in accordance with the verification so as to produce an output from the system.

Abstract: An improved method of transferring burst data in a microprocessor is described. The improvement lies in the burst ordering of the data items to be referenced. The original address is selected as the data item that the user initially wants to access. Subsequent addresses in the burst are generated according to a mathematical algorithm. The algorithm generates the remaining addresses as a function of the internal bus width, the external memory/bus line size and the original address. Using the burst sequence of the present invention, memories/buses of different widths can be smoothly coupled to a microprocessor having a fixed CPU bus size (e.g., 32 bits).

Abstract: Efficient coding speech information for low rate (e.g., 600 bps) channels using a four frame superframe (SF) includes: (1) coding spectral information using alternative quantizers one of which is chosen for each superframe so that 3 bits/SF identify the optimal quantizer and 28-32 bits/SF contain the quantized spectral information; (2) coding pitch using 5 bits/SF if voiced and if unvoiced assigning the pitch bits to error correction; (3) coding energy using 9-12 bits/SF by a 4d vector quantizer (4dvQ); and (4) coding voicing using 3-4 bits/SF by a 4d VQ, for a total of 54 bits/SF including 1 sync bit and 0-1 error correction bits. When combined with a unique perceptual weighting scheme, output speech quality comparable to that of vocoders operating at almost four times the channel capacity is obtained.

Abstract: An inner product computing unit computes inner products of an input pattern whose category is unknown, and orthogonalized dictionary sets of a plurality of reference patterns whose categories are known. A nonlinear converting unit nonlinearly converts the inner products in accordance with a positive-negative symmetrical nonlinear function. A neural network unit or a statistical discriminant function computing unit performs predetermined computations of the nonlinearly converted values on the basis of preset coefficients in units of categories using a neural network or a statistical discriminant function. A determining section compares values calculated in units of categories using the preset coefficients with each other to discriminate a category to which the input pattern belongs.

Abstract: The process for detection and masking of bad frames in a coded speech signal resulting from channel transmission errors has been improved. The coded speech signal has a first group of bits comprising the most perceptually significant bits of the coded speech signal, a second group of bits comprising the second most perceptually significant bits and a third group of bits comprising the least perceptually significant bits. The coded speech signal is de-interleaved to obtain a first series of bits comprising the first and second group and a second series of bits comprising the third group of bits. The first series of bits are convolutionally decoded for recovering the first and second group of bits, with the first group of bits containing error protected bits. A CRC check is performed by sending the recovered bits of the first group to cyclic redundancy decoding means. The first group of bits is forwarded to speech decoder means if the CRC check is successful.

Abstract: Method and apparatus allows accurate detection of voice presence on a digitized communication line even in the presence of tone signals. The method includes analyzing digitized communication input signals by current blocks of 20ms, to define the stationary or non stationary state of any current block. Then an analysis on the states of the M last 20ms blocks allows the final decision on voice presence.

Abstract: A sequence processor for rapidly learning, recognizing and recalling temporal sequences. The processor, called the Katamic system, is a biologically inspired artificial neural network based on a model of the functions of the cerebellum in the brain. The Katamic system utilizes three basic types of neuron-like elements with different functional characteristics called predictrons, recognitrons and bi-stable switches. The Katamic System is clock operated, processing input sequences pattern by pattern to produce an output pattern which is a prediction of the next pattern in the input sequence. The Katamic System learns rapidly, has a large memory capacity, exhibits sequence completion and sequence recognition capability, and is fault and noise tolerant. The system's modular construction permits straightforward scaleability.

Abstract: Apparatus for efficiently interconnecting OEMI channels of a multiprocessor facility. A plurality of channel adapters are connected to individual channels from a plurality of processors. A supervisory interrupt driven microprocessor receives a link request from a channel adapter when the channel adapter has determined that two logical adapters are in an appropriate architected state. The microprocessor will assign a data bus to channel adapters involved in a link request if certain criteria is met by said link requests, signifying an efficient transfer between said channel adapters is likely.

Abstract: A method and apparatus to improve computer bus access time. A bus is described which has sequential control states and fixed transaction times. Without the invention, arbitration may be delayed as the bus sequences through control states. With the invention, arbitration is immediate if the bus is idle. When any transaction is initiated, a counter is initialized to the number of control states in the standard transaction time. If the counter reaches zero, the bus is idle. If the bus is not idle, a sequence of bus control states is repeated. If the bus is idle, the bus is forced to remain in an arbitration state, thereby enabling any subsequent arbitration to take place immediately.

Abstract: A method and apparatus for the design of a robust vector quantizer is disclosed. The initial output vector set is equal to the centroid of a training sequence of input vectors. A neural-network simulation and neighborhood functions are utilized for splitting and optimizing the output vectors. In this manner, the entire output vector set is sensitive to each input vector and therefore optimal output vector locations with respect to specified distortion criteria are obtained. The resulting vector quantizer is robust for the class of signals represented by the training sequence.

Abstract: An expert system for the design and analysis of experiments includes a descriptive mathematical model of the experiment under consideration. From this mathematical model, expected mean squares are computed, tests are determined, and the power of the tests computed. This supplies the information needed to compare different designs and choose the best possible design. A layout sheet is then generated to aid in the collection of data. Once the data has been collected and entered, the system analyzes and interprets the results.

Abstract: A request is made by a system in a first logical partition, within a logically partitioned data processing system, to dynamically change the I/O configuration of the host system in a way that affects a system in a second logical partition. The hypervisor intercepts the request, ensures the serialization of such dynamic I/O requests, and allows dynamic reconfiguration to proceed. Subsequently, the hypervisor determines the effect of the reconfiguration on the second partition, and notifies the second partition of the change.

Abstract: A priority assignment method and device are set forth for assigning a priority to a selected speech frame coded by a linear predictive coder based on at least two of: an energy of the speech frame, a log spectral distance between a frame and a frame immediately previous, and a pitch predictor coefficient for the selected speech frame. The invention protects against loss of perceptually important and hard-to-reconstruct speech frames.

Abstract: A system is described that includes an arithmetic logic unit that senses the presence of a circuit module in a connector, wherein one type of circuit module, if present, automatically provides a set of signals on a predetermined pin set that indicates characteristics of the circuit module. The system also includes circuitry that enables the determination of the presence of other types of pluggable circuit modules in the connector. The circuitry comprises a latch circuit for holding a received address for the circuit module. In the received address, a preset field of bits is present which identifies a field in a status register. The status register stores n fields of information defining the characteristics of the pluggable circuit module and is responsive to the preset field of bits to provide signals on the predetermined pin set indicating the information.

Abstract: In a bus adapter coupling a system bus and an I/O bus which operate at different speeds and contain a plurality of devices, a method by which an arbiter in the bus adapter prevents contention for ownership of both buses by a device on either of the buses. The method includes the steps of sampling each of the devices requesting ownership of said buses and asserting a bus grant to one of the devices on one of the buses based on its assigned priority number. The method also includes the step of waiting for the device granted the bus to send an acknowledge signal to display ownership of the buses and for each of the devices not on the bus containing the device granted the bus to see the acknowledge signal before resampling and reasserting a new bus grant to another of the requesting devices.

Abstract: A register system for facilitating point of sale transactions of any of a plurality of products, each of the products having a bar code encoded product identification associated therewith, is disclosed. The register system comprises a central computer for storing data representing a sales price for each of the products, a plurality of distributed point of sale registers coupled to the central computer, a bar code reader, operatively associated with each of the registers, for scanning the bar code encoded product identification from the products. Each register is responsive to the scanned product identification and communicates with the central computer for transferring to the register associated with the bar code reader the sales price for the selected one of the products. The register system includes a bidirectional card reader for reading data stored as a plurality of sequential multi-bit characters on a magnetic stripe on a card.

Abstract: A neural network content-addressable error-correcting memory system is disclosed including a plurality of hidden and visible processing units interconnected via a linear interconnection matrix. The network is symmetric and all self-connections are not present. All connections between processing units are present, except those connecting hidden units to other hidden units. Each visible unit is connected to each other visible unit and to each hidden unit. A mean field theory learning and retrieval algorithm is also provided. Bit patterns or code words are stored in the network via the learning algorithm. The retrieval algorithm retrieves error-corrected bit patterns in response to noisy or error-containing input bit patterns.