Abstract: In an integrated circuit microprocessor, an M-bit priority encoder circuit indicates the highest priority bit position that is set in a first portion of an N-bit (N generally being greater than M) data word and provides control information regarding the number of bits that are set. If more than one bit is set, the highest priority bit is reset, the first portion is re-analyzed, and highest priority bit information and control information are again provided. If only one bit or no bit is set in the first portion, a second portion is analyzed, and highest priority bit information and control information regarding the second portion is provided. Analysis of the second portion, and of any subsequent portions, continues in similar fashion until no further bit positions are determined to be set in the data word.

Abstract: A voice-based security system requires that a series of utterances to be uttered by the requester contain at least one repeated utterance. The system compares a representation of each instance of the repeated utterance as uttered by the requester to both a prestored template for the utterance and to each representation of the other instances of the utterance as uttered by said requester. The requester is authenticated only if each representation of the repeated utterance as uttered by said requester matches the prestored template and the representations of the repeated utterance as uttered by said requester do not match each other to such a high degree that they are deemed to have been mechanically generated.

Abstract: A recognizing and judging apparatus includes a plurality of recognition units organized in a multi-layered hierarchical network structure. Some recognition units include a signal input section, a quantizer for performing a quantization according to a signal inputted from the signal input section, and a path selecting section having at least one path input terminal; and at least one path output terminal. The path selecting section performs a selection of paths according to an output of the quantizer.

Abstract: A fast arbiter for handling a large number of types of resources with multiple instances of each type of resource is provided. During a first cycle a request logic circuit broadcasts a request for a preselected type of resource onto a broadcast medium. During a second cycle a grant logic circuit broadcasts a queue position onto the broadcast medium for the preselected type of resource. Also, during the second cycle the request logic circuit stores the queue position. After an asynchronous wait for an instance of the requested type of resource to become free, a third cycle begins wherein the first grant logic circuit broadcasts an indication that a free instance of the preselected type of resource is available. During a fourth cycle the requester is granted access to the free instance of the preselected type of resource.

Abstract: This disclosure relates to personal computer systems, and more particularly to a personal computer which provides for interrupt redirection of the activity of a microprocessor. The personal computer system has a multichannel bus for transferring data, a microprocessor for manipulating data and coupled to the bus, and a plurality of input/output devices coupled to the bus for receiving and delivering data for manipulation by the microprocessor. Each input/output device is capable of generating a logical interrupt signal indicative of a request for access to the microprocessor and of being remotely reset to a non-interrupt condition, and all of the devices deliver their logical interrupt signals through a common physical channel of the bus.

Abstract: A circuit (14) to evaluate a plurality of fuzzy logic rules in a data processor (10) in response to a single "REV" software instruction. The REV instruction evaluates the rules stored in a memory (32) to determine a rule strength of each. Antecedents are separated from consequences of each of the rules by a buffer address. To evaluate the antecedents, an ALU (52) subtracts an antecedent in memory (32) from a current antecedent stored in an accumulator (58). Subsequently, a swap logic (46) provides control information to assign a minimum value as a rule strength of the rule. Similarly, a maximum rule strength is required during evaluation of the consequences. ALU (52) subtracts a consequence in memory (32) from a consequence stored in accumulator (58). Depending on a result, swap logic (46) provides control information to assign a maximum rule strength to the consequences of the evaluated rule.

Abstract: A method and apparatus for finding the best or near best binary classification of a set of observed events, according to a predictor feature X so as to minimize the uncertainty in the value of a category feature Y. Each feature has three or more possible values. First, the predictor feature value and the category feature value of each event is measured. The events are then split, arbitrarily, into two sets of predictor feature values. From the two sets of predictor feature values, an optimum pair of sets of category feature values is found having the lowest uncertainty in the value of the predictor feature. From the two optimum sets of category feature values, an optimum pair of sets is found having the lowest uncertainty in the value of the category feature. An event is then classified according to whether its predictor feature value is a member of a set of optimal predictor feature values.

Abstract: A user-friendly expert system with new types of knowledge bases is disclosed. The major new components in the invented expert system are: A stored knowledge base in the form of an array, an input knowledge base in the form of a truth table or in some other user-defined forms, a transfer engine being a built-in computer program transferring the input knowledge base to the stored knowledge base, and an automatic inference engine being a built-in computer program reasoning with the stored knowledge base by a double loop. No matter what the size of the input knowledge base is, and no matter what the size of the input knowledge base is, and no matter what kind of knowledge is stored in it, the double loop always processes the inference automatically, and no compilation is necessary. Therefore, the inference engine is called the automatic inference engine and the system is called the automatic expert system.

Abstract: Arbitration is performed among a plurality of users for access to a shared resource in a system of the kind in which the users arbitrate by placing arbitration signals on a line and subsequently comparing their arbitration signals with a signal appearing on the line, by providing the users with independently operating clocks, and controlling the progression of the arbitration based on timing provided by the clock of at least one of the users. The progression of the arbitration thus does not depend upon a single master clock, or upon synchronizing the individual user clocks.

Abstract: A syntax converting apparatus performs conversions between an abstract syntax and a transfer syntax in a presentation layer, defined by an Open Systems Interconnection (OSI). The presentation layer determines the syntax, which describes application processes, and exchanges this syntax with a syntax to be transferred. The syntax converting apparatus is capable of separately decomposing presentation protocol data units (PDUs), which are defined by two different standards, for example, Standard x and Standard y. This is accomplished using a decoding and a decomposing unit in the presentation layer. The decoding unit decodes data strings encoded in accordance with ISO 8825 ASN.1 Basic Encoding Rules, and the decomposing unit decomposes this decoded data with each of the protocol specification units, describing the abstract syntax thereof.

Abstract: A multiple bus architecture for flexible communication between processors, memory subsystems, and specialized subsystems over multiple high performance communication pathways. The multiple bus architecture enables flexible communication between processors and devices coupled to a multiprocessor bus, a system interconnect bus, an external bus, an input/output bus, and a memory subsystem. Processor modules coupled to multiprocessor bus slots access the memory subsystem over the multiprocessor bus. System interconnect modules coupled to system interconnect bus slots access the memory subsystem via the system interconnect bus, and the multiprocessor bus. Processor modules coupled to multiprocessor bus slots access devices on the external bus via the system interconnect bus.

Abstract: An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurality of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.

Abstract: The present invention provides a test and set bypass mechanism which allows access to a semaphore while eliminating memory bandwidth degradation due to the traditional "spin-locking" problem. Generally, a storage and comparison structure in a processor, such as a content addressable memory (CAM), is used to store the address of the semaphore whenever it is requested. Thus, the process/processor, or other processors in a multiprocessor system, then need only check to see if the semaphore address is present in its respective storage and comparison structure. Consequently, there is no need to make multiple memory transactions for failed access of the semaphore, and hence, effective memory bandwidth is increased.

Abstract: A code excited linear prediction (CELP) type speech signal coding system is provided, a code vector obtained by applying linear prediction to a vector of a residual speech signal of white noise is stored in a code book. A pitch prediction vector obtained by applying linear prediction to a residual signal of a preceding frame is given a delay corresponding to a pitch frequency and added to the code vector. Use is made of an impulse vector obtained by applying linear prediction to a residual signal vector of impulses having a predetermined relationship with the vectors of the white noise code book. Variable gains are given to at least the above code vector and impulse vector, a reproduced signal is produced, and this reproduced signal is used for identification of the input speech signal. Thus, a pulse series corresponding to the sound source of voiced speech sounds is created.

Abstract: A control board connected to a main body of a computer, which has access to an optical recording medium through an optical recording medium read/write device, and for controlling and enabling the optical recording medium read/write device to have access to the optical recording medium in the same manner as an existing magnetic disk device and the like have with respect to a magnetic medium. This control board is composed of a directory development processing station, various types of interface processing stations, a retrieval processing station, a data transfer/receiving processing station, a data input/output processing station and a directory update processing station. It is possible to have access as easily to the optical recording medium as to other existing media by using commands, I/O functions, and so on in the computer body.

Abstract: A data processing system of the neural network type. The system recognizes a predetermined shape by providing some connections that are inhibitory between a plurality of neurons in a neural layer of the neural network. If data is found in the inhibitory area, it makes it harder for the neurons in the correct area to fire. Only when the neurons in the correct area fire is the predetermined shape recognized.

Abstract: A reconfigurable fuzzy cell comprising a digital control programmable gain operation amplifier, an analog-to-digital converter, an electrically erasable PROM, and 8-bit counter and comparator, and supporting logic configured to achieve in real-time fuzzy systems high throughput, grade-of-membership or membership-value conversion of multi-input sensor data. The present invention provides a flexible multiplexing-capable configuration, implemented entirely in hardware, for effectuating S-, Z-, and PI-membership functions or combinations thereof, based upon fuzzy logic level-set theory. A membership value table storing "knowledge-data" for each of S-, Z-, and PI-functions is contained within a nonvolatile memory for storing bits of membership and parametric information in a plurality of address spaces. Based upon parametric and control signals, analog sensor data is digitized and converted into grade-of-membership data. In situ learn and reconfiguration modes of operation are also provided.

Abstract: A signal processing apparatus for controlling an object includes an input unit, a neural network, an output unit, a teaching unit, and an error signal generator for generating a teaching signal that makes the neural network learn in real time. An error signal generator generates an error signal from the teaching signal and information contained in the network output signal. The error signal controls the neural network so that the control output signal has correct control information with respect to the output signal from the controlled object.

Abstract: Methods and an arrangement providing improved expert system performance. A mathematically based method is used in building a rule base that guarantees a complete and consistent rule set, providing an aid for identifying missing rules. The method is used in recognizing input variable patterns in parallel to provide rapid inferencing. An arrangement based on the method is given for a content addressable memory capable of returning an address of an executable routine for each rule of a rule set given the system state variables. The method is employed to provide associative program control, in which program control flow adapts to changing system state variables. A method is described for associative database management, using the new content addressable memory arrangement.

Abstract: A protocol for communicating messages between a manager for a computer system and a remote facility asynchronously connected with the system manager and a method for exchanging messages using the protocol. The protocol determines whether the system manager is ready to exchange messages with the remote facility, determines whether the remote facility is ready to exchange messages with the system manager and exchanges messages between the system manager and the remote facility. To exchange messages, a command message which includes a first field for identifying a command transmitted by the command message and a second field for identifying the command message is transmitted. In response, a command reply message which includes a first field for identifying the command to which the command reply message is in response to, a second field for matching the command response message to the command message and a third field for transmitting a response to the command message is transmitted.