Abstract: An optimization apparatus using a layered neural network having an input layer formed of input units and supplied with input data and an output layer formed of output units connected to the individual input units with specified synaptic weights, which comprises a calculator circuit for calculating, for each output unit, the degree of similarity between the input data and the synaptic weight as well as the evaluation function value by causing the optimization problem to correspond to the fired units in the output layer, a detector for detecting the best matching optimum output unit on the basis of the output of the calculator circuit, and a self-organization circuit for changing the synaptic weights of a group of the output units associated with the optimum unit detected by the detector.

Abstract: A speech-recognition system includes a speech-recognition arrangement (1) and a learning device (5) for adapting the speech-recognition arrangement to the characteristic pronunciation of a given speaker during an adaptive learning mode. Certain words are applied during a learning procedure to the speech-recognition arrangement via a keyboard and, in addition, the sound signals associated with these certain words and originating from the given speaker are fed-in via a microphone. The sound signals corresponding to a spoken text are fed into the speech-recognition arrangement via a storage medium which can be scanned by a reproducing device. The reproducing device may be implemented in the form of a recording and reproducing device (7). The sound signals which are fed in to the system during a learning procedure of the speech-recognition arrangement are first recorded onto the storage medium and immediately thereafter are scanned from the storage medium and are fed into the speech-recognition arrangement.

Abstract: In the system of the present invention, the limitations imposed by the physical limitations of the DMA controller are overcome by storing the channel control blocks in external memory. The DMA controller is programmed to reference a particular address of external memory when a predetermined bit in the current channel control block is set. The DMA controller will then perform a memory read operation on the area of memory referred to by that address in order to store the retrieved channel control block at a location previously utilized by a earlier channel control block. This reading process will continue until the bit is reset, at which time the DMA operation is complete. Dynamic chaining is accommodated whereby the channel control blocks can be dynamically changed during the DMA access to provide a flexible I/O system. Furthermore, a method and apparatus for implementing dynamic chaining without incurring race conditions is described.

Abstract: An apparatus for preventing bus contention among a plurality of data sources is described which creates signals to be used to disable two of three data sources which share a common bus immediately prior to a bus access cycle. The circuit employs a negative edge triggered flip-flop. This flip-flop generates disable signals which are shifted in phase by 90.degree. with respect to the bus access clock signal. These signals are active one-quarter of a clock cycle before a new bus cycle begins. The early disable serves to clear the bus for access by substantially eliminating the possibility that a slowly responding disabled data source is still active while a quickly responding enabled data source has just become active. The early disabling of the data signals does not result in loss of data. When all data sources on the bus are turned off, a high signal simply goes higher and a low signal rises slowly.

Abstract: Method and apparatus for improving an efficiency of solution of constraint-satisfaction type problems performed with a digital computer. A method includes the steps of creating a data structure having storage allocated for a plurality of entries, each of the entries having a plurality of attribute fields, including a Binding.sub.-- set attribute, a Potential.sub.-- savings attribute and an Accumulated.sub.-- savings attribute. The method further includes a step of inserting entries into the data structure in response to an occurrence of a failure path identified during a backtrack search of a search tree structure. The method also includes a step of examining the entries of the data structure during a backtrack search in order to avoid paths of the tree structure that are repetitively identified to be failure paths.

Abstract: A fuzzy reasoning computer having a multi-stage construction is disclosed which includes a primary fuzzy reasoning computer at a rank having a reasoning system for producing a reasoned result, at least one child fuzzy reasoning computer at a lower rank having a reasoning system for producing a reasoning result and a system for providing the reasoning results of the at least one child fuzzy reasoning computer to the reasoning system of the primary fuzzy reasoning computer in such a manner that the reasoning performed by the primary fuzzy reasoning computer is assisted by the at least one child fuzzy reasoning computer.

Abstract: An electronic device comprises a first memory for storing a plurality of words which are to be displayed on a display coupled to the first memory and a second memory for storing a plurality of voice information codes each corresponding to a portion of a different one of the plurality of words stored in the first memory. The second memory also stores a specific code for distinguishing each of the plurality of voice information codes and stores each of the plurality of voice information codes and the specific code so that the voice information codes and the specific code are alternatively read out.

Abstract: A protocol for carrying out transactions in a multiple-processor computer system comprises: dividing the transaction cycle into four quadrature states, an arbitrate state, an I/O state, a slave address state and a virtual memory state. The protocol enables the processors to determine before arbitrating whether the memory device is busy, which reduces the number of "busied" transactions.

Abstract: A microprocessor includes an internal memory and various subcomponents that allow the microprocessor to operate out of its internal memory during periods of time in which it does not have use of an external bus via which it may operate out of an external memory.

Abstract: A virtual memory management arrangement translates a process virtual address of an item of data in an array of data into a physical address for use in accessing a memory. A virtual address translation portion forms, in response to a process virtual address, an array virtual address including a sub-array identifier identifying a sub-array in the array and an array virtual offset identifying a virtual storage location in the sub-array. A physical address translation portion forms, in response to the array virtual address, a physical address for use in accessing a memory.

Abstract: A clock circuit (12) normally couples clock pulses to a microprocessor (11), which is capable of accessing memory devices (13,14) having different access times. Access of a "slow" memory device 14 is detected by the clock circuit, and in response thereto, one or more clock pulses are not coupled to the microprocessor. This suspends operation of the microprocessor for a suitable amount of time so that the microprocessor reads valid data from the slow memory device. The number of clock pulses blocked from reaching the microprocessor can be set in a delay circuit (28) in the clock circuit.

Abstract: A method is provided for use in a computer system, the method for performing callbacks to a first calling thread that has made an RPC to a second called thread comprising the steps of: creating at least one respective helper thread in the address space of the second called thread; and for each respective created helper thread, providing a respective thread-specific identifying mechanism for identifying the first calling thread.

Abstract: Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

Abstract: A method and apparatus for transferring data between two storage media, and is used in an illustrative embodiment to transfer data between two storage media in a shadow set, the storage media being accessible to one or more host processors. The method of the preferred embodiment includes the steps of: A. receiving a command from one of the host processors, the command specifying data to be transferred from a first storage medium to a second storage medium; B. transferring the data specified in the command received from the host from the first storage medium to the second storage medium in a series of subtransfers, each of the subtransfers transferring a portion of the data; and C. processing one or more I/O requests to the shadow set received from one or more host processors by, for each received I/O request: a. implementing the I/O request if the I/O request does not involve a section of the shadow set currently involved in one of the subtransfers; and b.

Abstract: An ID processing dedicated SCSI bus interface logic circuit comprising a self ID decoder for decoding a self ID input; a priority encoder for encoding the highest priority ID on a SBI data bus; an ID Win comparator for comparing the self ID input with an output from said priority encoder to generate an ID win signal; a multiplexer for multiplexing the output from the priority encoder and a target ID input; a target ID decoder for decoding an output from the multiplexer; an NOR gate for NORing outputs from the self ID decoder 11 and from the target ID decoder every bit; a driver for arbitrating an output from the NOR gate to the SBI data bus; an IDOK comparator for comparing the output from the NOR gate with the ID on the SBI data bus to generate a signal IDOK; and a latch for latching the output from the priority encoder in response to an ID latch clock from a host computer to output a target ID selection signal.

Abstract: A neural network processing apparatus calculates an average of the absolute values of differences between the output values of all neurons and a center value whenever the output value of all neurons change, and calculates the difference between the average and the previous average. If the average is larger than a threshold or the previous average, the gain of a function in the network is decreased. If the average is smaller than the threshold or the previous average, the gain of the function is increased. Then the controlled function is set to each neuron and the neural network is activated repeatedly to correctly identify an unknown multivalued image pattern.

Abstract: A multiprocessor system includes a plurality of central subsystem (CSS) units, a plurality of memory units and input/output units which connect in common to a system bus for transferring requests between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. A private bus (P bus) connects all of the CSS units and memory units in common for high speed block data transfers. Each CSS unit includes input circuits which couple to the priority network for detecting when the system bus is in an idle state. P bus logic circuits couple to the P bus and generate a transfer request in response to a request from its CSS unit only when the P bus is detected to be in an idle state. The idle signals from both buses are used to generate a system bus request for P bus access only when both buses are in an idle state so as to eliminate the need to contend for system bus use.

Abstract: A method of breaking up a vocal signal into binary frames of a predetermined duration. The frames are grouped together in packets of successive frames by associating a predictive filter with each frame of a packet. Furthermore, the coefficients of each predictive filter are quantified by taking into account the stable or non-stable configuration of the vocal signal.

Abstract: Features are extracted from a sampled input signal by performing first linear predictive analyses of different first orders p on the sample values and performing second linear predictive analyses of different second orders q on the residuals of the first analyses. An optimum first order p is selected using information entropy values representing the information content of the residuals of the second linear predictive analyses. One or more optimum second orders q are selected on the basis of changes in these information entropy values. The optimum first and second orders are output as features. Further linear predictive analyses can be carried out to obtain higher-order features. Useful features are obtained even for nonstationary input signals.

Abstract: An apparatus for synchronously generating a first clock signal in a first circuitry and a second clock signal in a second circuitry of a data processing system is described. A clock generating circuitry generates a global clock signal. A transmission line transfers the global clock signal from its first end to its second end and includes a midpoint between the first end and the second end. A first clock signal generation circuit is coupled at a first point between the first end and the midpoint and a second point between the midpoint and the second end. The first and second points have the same line length to the midpoint. The first clock signal generation circuit generates the first clock signal at a first timing point which is halfway between the global clock signal with a first propagation delay from the first end to the first point and the signal with a second propagation delay from the first end to the second point.