Abstract: Memory systems and memory programming methods are described.

Abstract: Embodiments of the present invention provide systems and methods for generating a set of test cases using a base test program. The base test program may be used as both a functional drive and as a performance measuring test case. From the base test program, additional key and value pairs may be added to the base test program to force specific test scenarios.

Abstract: A semiconductor memory device includes a first inverter, a second inverter, a first and second inner access transistors, and a first and second outer access transistors. The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor (PL2) and a second pull-down transistor, and the first inverter and the second inverter forms a latch circuit. The first and second inner access transistors and the first and second outer access transistors are electrically connected to the latch circuit, and channel widths of the second inner access transistor and the second outer access transistor are different from each other.

Abstract: A nonvolatile memory device includes a memory cell array that stores data, and control logic. The control logic is configured to control a read operation, a program operation, or an erase operation on the data. The control logic is configured to detect a first power noise based on one of voltage sources to be provided to the memory cell array and a first reference voltage and detect a second power noise based on the one voltage source of the voltage sources and each of the first reference voltage and a second reference voltage. The control logic is configured to determine whether to perform at least one of an operation period of the read operation, an operation period of the program operation, or an operation period of the erase operation, based on whether at least one of the first and second power noises is detected.

Abstract: A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.

Abstract: A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.

Abstract: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.

Abstract: An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled with the plurality of memory devices, configured to determine a range of read reference voltages having a plurality of read reference voltages, the read reference voltages achieving a minimal rBER; calculate an optimal read reference voltage in accordance with at least the range of read reference voltages; achieve a rBER in accordance with at least the optimal read reference voltage; and execute error correction process with at least the optimal read reference voltage.

Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.

Abstract: A storage system and method for handling overheating of the storage system are disclosed. The method comprises determining whether a temperature sensed by a temperature sensor is above a first threshold temperature; and in response to determining that the temperature sensed by the temperature sensor is above the first threshold temperature, lowering a voltage supplied by a power supply to one or more components in the storage system comprising transistors, wherein lowering the voltage supplied to the one or more components reduces temperature by reducing leakage current of the transistors.

Abstract: Methods of operating a memory include receiving a plurality of digits of data, determining a value of the plurality of digits of data, and selecting a function to represent the value of the plurality of digits of data. The selected function is a function of a cell number of each memory cell within a grouping of memory cells. The methods further include determining a desired threshold voltage of a particular memory cell of the grouping of memory cells corresponding to the value of the selected function for the cell number of the particular memory cell, and programming the particular memory cell to its desired threshold voltage.

Abstract: Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.

Abstract: A semiconductor memory device includes a memory cell array, a read/write circuit and a control logic. The memory cell array includes a plurality of memory cells. The read/write circuit is configured to write data to the memory cell array or read data from the memory cell array. The control logic is configured to control the read/write circuit to perform a read/write operation for the memory cell array. The memory cell array includes a plurality of memory blocks, and each of the memory blocks includes a plurality of sub-blocks. During an operation of erasing a sub-block in a memory block, the control logic selects a sub-block to be erased regardless of a sequence in which the sub-blocks have been programmed, and determines an erase verify voltage based on a position of the selected sub-block.

Abstract: A magnetic memory device is provided. The magnetic memory device includes a memory circuit comprising a first tunnel magnetoresistive element and a second tunnel magnetoresistive element coupled in series. An input node of the magnetic memory device is coupled to the first tunnel magnetoresistive element, wherein the input node is configured to receive a voltage signal. The first tunnel magnetoresistive element initially holds a first resistance value, wherein the first tunnel magnetoresistive element is short-circuited to hold a second resistance value after the voltage signal is received by the input node. End nodes of the memory circuit are coupled to defined voltages in a read mode. The magnetic memory device further includes a read-out circuit configured to measure a voltage at a sensing node in the read mode. The sensing node is interconnected between the first tunnel magnetoresistive element and the second tunnel magnetoresistive element.

Abstract: Embodiments are provided that include a method including providing a first voltage to a selected memory cell and providing a second voltage to the selected memory cell during an operation. The first voltage is greater in magnitude than the second voltage and the first voltage is applied for a shorter duration than the second voltage. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.

Abstract: A magnetic memory includes: a first and second terminals; a conductive layer including first to fourth regions, the first and fourth regions being electrically connected to the first and second terminals respectively; a first magnetoresistive element including: a first and second magnetic layers; a first nonmagnetic layer between the first and second magnetic layers; and a third terminal electrically connected to the first magnetic layer; a second magnetoresistive element including: a third and fourth magnetic layers; a second nonmagnetic layer between the third and fourth magnetic layers; and a fourth terminal electrically connected to the third magnetic layer; and a circuit configured to apply a write current between the first terminal and the second terminal and apply a first and second potentials to the third and fourth terminals respectively to write the first and second magnetoresistive elements, the first and second potentials being different from each other.

Abstract: Unlike prior RAM-based shift register circuits, the presently-disclosed shift register circuit does not require control circuits to generate write and read address signals. Instead, the presently-disclosed shift register circuit utilizes a portion of RAM to store and provide the write and read address signals. The write and read addresses are output from the data output port of the RAM, and received by the write and read address ports of the RAM. Advantageously, the presently-disclosed shift register circuit requires less area to implement because the need for write and read control circuits is eliminated.

Abstract: Multiple reads of memory cells of a flash memory device are initiated at different read levels to obtain raw data. For each different read level, multiple decoding operations are initiated to decode the raw data, each decoding operation using a different one of a plurality of sets of decoding information associated with the different read level. Decoding success rates are determined for one or more of the plurality of sets based on the one or more of the plurality of sets being used to successfully decode data and, for each different read level, an order of the plurality of sets is determined based on the determined success rates. A selected set of decoding information is selected for use in decoding raw data obtained from a read performed at a respective read level based on the respective read level and the set order of the plurality of sets for the respective read level.

Abstract: Apparatuses and methods for reading memory cells are described. An example method includes sharing a first voltage to increase a voltage of a first sense line coupled to a first capacitor plate of a ferroelectric capacitor of a memory cell, sharing a second voltage to decrease a voltage of a second sense line coupled to a second capacitor plate of the ferroelectric capacitor of the memory cell, sharing a third voltage to increase the voltage of the second sense line, and sharing a fourth voltage to decrease the voltage of the first sense line. A voltage difference between the first sense line and the second sense line that results from the voltage sharing is amplified, wherein the voltage difference is based at least in part on a polarity of the ferroelectric capacitor.

Abstract: A memory device includes at least one memory cell which contains a resistive memory element having a conductive metal oxide located between a first electrode and a second electrode. The conductive metal oxide has a concentration of free electrons in thermodynamic equilibrium in a range from 1.0×1020/cm3 to 1.0×1021/cm3. A method of operating the memory device includes redistributing electron density to set and reset the device. An oxide barrier layer may be located between the conductive metal oxide and the second electrode.