Abstract: A memory device includes a memory cell that is configured to store a data bit, comprising at least one read transistor that is configured to form either a discharging path or a leakage path when the data bit is read; a conductive line coupled to the read transistor; and at least a first track transistor, coupled to the conductive line, and configured to provide a first current signal having a first current level that tracks a second current level of a second current signal, wherein the second current signal is provided when either one of the discharging and leakage paths is formed, and wherein the first the second current signals are used to determine a logical state of the data bit.

Abstract: Automated test procedures, carried out under software control, can be employed to test a device, testing individual pins, and/or groups of pins, to detect and diagnose or characterize various types of failures. A distributed FA system includes a shared database for device definitions, test setups, and test results. Test platforms provide I/O curve tracing which can provide both a qualitative visual representation and a quantitative measured performance. The disclosed system enables and exploits front line testing of devices in the field. Response to the customer can be nearly immediate. Eliminate “false returns” by differentiation of use versus a real quality issue.

Abstract: An integrated circuit (IC) can dynamically manage memory communication paths between multiple processors and multiple memory modules. The IC can include upstream logic that performs data conversion and provides memory communication paths between each processor and a corresponding upstream port. An interconnect layer in the IC can be electrically coupled to the upstream ports to multiple downstream ports. An interconnect management processor electrically coupled to the interconnect layer can respond to received commands by executing an allocation program stored in a read-only memory (ROM) that dynamically establishes and terminates memory communication paths between the upstream ports and the downstream ports. A memory interface layer in the IC can be electrically coupled to the downstream ports and to the memory modules, and can provide, through corresponding memory physical interfaces, memory communication paths between the multiple downstream ports and corresponding memory modules.

Abstract: A voltage controlling circuit may include a first voltage terminal, a second voltage terminal and a plurality of Ovonic threshold switch (OTS) units. The second voltage terminal may have a voltage different from that of the first voltage terminal. The OTS devices may be connected between the first voltage terminal and the second voltage terminal. The OTS units may be serially connected with each other.

Abstract: A method of sensing a resistance change memory device includes preparing a memory cell including a variable resistance element storing different data on the basis of a variable resistance, and a switching element connected to the variable resistance element and performing a threshold switching operation, measuring a first cell current by applying a first read voltage to the memory cell, the first read voltage being selected in a threshold-sensing range of a current-voltage characteristic curve of the memory cell, measuring a second cell current by applying a second read voltage to the memory cell, the second read voltage being selected in a resistance-sensing range of the current-voltage characteristic curve, and when at least one of the first cell current and the second cell current is greater than a corresponding reference current, outputting a data signal having a first logic value as data stored in the memory cell.

Abstract: A semiconductor device includes a first row address generation circuit and a second row address generation circuit. The first row address generation circuit generates a first row address for refreshing memory cells connected to word lines included in a first up block and a second up block from a refresh command and an active signal in response to a period selection signal and a first period signal. The second row address generation circuit generates a second row address for refreshing memory cells connected to word lines included in a first down block and a second down block from the refresh command and the active signal in response to the period selection signal and a second period signal.

Abstract: A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially reduce the level of current flowing through the MTJ with rise in temperature, as experienced by the MTJ. The first circuit is operable to adjust a slope of a curve representing current as a function of temperature and the second circuit is operable to adjust a value of the current level through the MTJ to maintain current constant or to reduce current when the temperature increases. This way sufficient current is provided for the MTJ at different temperatures to prevent write failure, over programming, MTJ damage and waste of current.

Abstract: Systems, circuits, and methods are disclosed for charge sharing. In one such example system, a first line is configured to be driven to a first voltage representative of data to be placed on the first line and then precharged to a first precharge voltage. A second line is configured to be driven to a second voltage representative of data to be placed on the second line and then precharged to a second precharge voltage. A charge sharing device is coupled between the first line and the second line. The charge sharing device is configured to selectively allow charge from the first line to flow to the second line after the first and second lines are driven to the respective first and second voltages representative of data to be placed on the respective lines.

Abstract: Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Abstract: A digital-to-analog converter (DAC) and memory device includes an array of memory cells including resistive memory elements programmable between a high resistive and low resistive state. In implementations the array of memory cells is segmented into unary and binary coded sub-arrays. The device includes a binarizer configured to couple to the memory array to assign binary weights, or segmented unary and binary weights, to currents through a plurality of memory cells or voltages across a plurality of memory cells. The memory device further includes a summer to sum the weighted outputs of the binarizer. A current to voltage converter coupled with the summer generates an analog output voltage corresponding with digital data stored in a plurality of memory cells.

Abstract: A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.

Abstract: Apparatuses and techniques are described for reducing or eliminating program disturb in non-volatile storage. In one aspect, the ramp rate of a voltage applied to a dummy word line is reduced during programming of edge word lines. In one embodiment, a slower than normal ramp rate is used for a dummy word line when the word line selected for programming is an edge word line, but a normal ramp rate is used for the dummy word line when the word line selected for programming is a middle word line.

Abstract: A method for minimizing skew in a High Bandwidth Memory (HBM) device is provided. The method includes grouping a plurality of information bits of the HBM device into at least two groups of information bits, wherein the plurality of information bits includes a plurality of data bits and a plurality of control bits, and the plurality of information bits are grouped such that each group of the at least two groups includes at least one control bit and the at least two groups form a byte of data. The method further includes delaying the plurality of information bits of each group of the at least two groups during a data transfer operation to minimize the skew between the at least two groups of information bits.

Abstract: Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write operation will always be successful regardless of whether the read and write row select are to the same row.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include free layer having a variable magnetization direction; a tunnel barrier layer formed over the free layer; a pinned layer formed over the tunnel barrier layer and having a pinned magnetization direction; an exchange coupling layer formed over the pinned layer; and a magnetic correction layer formed over the exchange coupling layer, wherein the magnetic correction layer comprises a first magnetic layer, a spacer layer and a second magnetic layer that are sequentially stacked, and the first magnetic layer has a saturation magnetization smaller than a saturation magnetization of the second magnetic layer.

Abstract: Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.

Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.

Abstract: Technology for performing read operations in a memory device or system is described. The device or system can include an array of memory cells. The device or system can include a first decode circuit, and can further include a second decode circuit. The device or system can include a voltage regulator configured to perform a read operation by providing, based on one or more signals received from at least one of the first decode circuit or the second decode circuit, a voltage to a selected plane or a selected sub-plane in the array of memory cells.

Abstract: A bitcell for storing a charge state, the bitcell including a spin hall metal for passing through a charge current, a magneto tunnel junction (MTJ) stack for generating and storing a non-volatile spin state corresponding to a binary bit in response to passage of the charge current through the spin hall metal, and for inducing the charge current corresponding to the non-volatile spin state in response to application of a read voltage, first and second write bitlines for sourcing the charge current through the spin hall metal in response to a write voltage being applied to both of the first and second write bitlines, and a read bitline for inducing the charge current through the spin hall metal in response to the read voltage being applied to the read bitline, and a first wordline and a second wordline for permitting a flow of the charge current through spin hall metal.