Abstract: A semiconductor memory device includes a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; and a control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information.

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

Abstract: A non-volatile memory may be resident in a data storage device. The non-volatile memory can consist of a rewritable in-place memory cell having a read-write asymmetry. The non-volatile memory may be divided into a first group of tiers with a selection module of the data storage device prior to adapting to an event by altering the non-volatile memory into a second group of tiers. The first and second groups of tiers being different.

Abstract: Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.

Abstract: The present disclosure relates to a dynamic random access memory (DRAM) array, which comprises a plurality of bit lines connectable, respectively, to at least two row buffers of the DRAM array. The two row buffers are respectively connectable to data input/output (I/O) lines and are configured to electrically connect the two row buffers to the bit lines and data I/O lines in a mutually exclusive manner.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.

Abstract: The present invention provides an electromagnetic conversion device, comprising: an intermediate layer and electrode layers located on both sides of the intermediate layer, wherein the intermediate layer is a magnetoelectric layer. The electromagnetic conversion device realizes the direct conversion of charge and magnetic flux, and thus can be used as a fourth fundamental circuit element, so as to provide a new degree of freedom for the design of electronic circuits and information function devices. In addition, the electromagnetic conversion device can be used as memory elements to form a nonvolatile magnetoelectric information memory.

Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is coupled to an element whose status is to be determined, and the first module is to receive an input current that increases over time. The second module is to perform a temporal derivative of a voltage across the element. The third module is to provide an output signal based on a current behavior of the element, according to a change in voltage as a function of a change in current.

Abstract: A semiconductor storage device includes a first memory area; a first selection circuit which selectively connects one of first lines to one of first bit lines of the first memory area, the first lines and the first bit lines extending in a first direction; a second memory area; a second selection circuit which selectively connects one of the first lines to one of second bit lines of the second memory area, the second bit lines extending in the first direction; and a third selection circuit which selectively connects one of the first lines to a global bit line and is arranged between the first selection circuit and the second selection circuit, and configured to select the first selection circuit and the second selection circuit. The first memory area, the first selection circuit, the third selection circuit, the second selection circuit, and the second memory area are aligned in this order in the first direction.

Abstract: A semiconductor device may include a division control circuit and a latch circuit. The division control circuit may be configured to divide an external clock to generate a first preliminary divided clock and a second preliminary divided clock. The division control circuit may be configured to output the first and second preliminary divided clocks or any one of the first and second preliminary divided clocks as first and second divided clocks. The latch circuit may be configured to latch an external control signal in response to the first and second divided clocks and configured to output latched signals as first and second latch control signals.

Abstract: A semiconductor memory device including: a first transistor connected between a first node and ground, the first transistor having a gate connected to a second node; a second transistor connected between the second node and ground, the second transistor having a gate connected to the first node; a third transistor connected between first and third nodes, the third transistor having a gate connected to the second node; a fourth transistor connected between second and fourth nodes, the fourth transistor having a gate connected to the first node; a fifth transistor connected between the first node and bit line, the fifth transistor having a gate connected to a word line; a sixth transistor connected between the second node and complementary bit line, the sixth transistor having a gate connected to the word line; and a circuit to reduce a gate-source voltage of the third or fourth transistor in a write operation.

Abstract: Disclosed are techniques for determining a threshold number of read operations on memory depending on one or more conditions of the memory. If a number of read operations for the memory meets the threshold number of read operations, a read reclaim operation can be performed to preserve data stored therein.

Abstract: SRAM structures are provided. A SRAM structure includes multiple SRAM cells arranged in multiple rows and multiple columns. The SRAM cells in the same row are divided into multiple groups. Each group includes a first SRAM cell and a second SRAM cell adjacent to the first SRAM cell. The first and second Vss lines and the first and second word-line landing pads are formed in a first metallization layer and extend parallel to a first direction. The third Vss line and the first word line are formed in a second metallization layer and extend parallel to a second direction. The first word-line landing pad is positioned within the rectangular shape of the first or second SRAM cell, and the second word-line landing pad is positioned within the rectangular shape of the second SRAM cell. The second metallization layer is positioned on the first metallization layer.

Abstract: A dual-port memory including a first memory array and at least one address decoder. The first memory array includes memory cells and two ports for each of the memory cells. The at least one address decoder generates word line signals for concurrent access to two ports of one or more cells of the memory cells in a same row of the first memory array. Each of the word line signals is generated to perform a read operation. Pulse widths of the word line signals for the read operations are proportional to a ratio of (i) a reference amount of cell current of a cell of a reference memory array to (ii) an amount of cell current of the one or more cells of the plurality of memory cells in a same row of the first memory array.

Abstract: A non-volatile memory cell stores 1.5 bits of data in three polarization states. The memory cell may have two ferroelectric layers and three electrodes. The energy bands of the ferroelectric layers are adjusted by providing two of the electrodes with different work functions. The difference in the work functions may be significant, such as at least 0.4-0.6 V or more. Two of the electrodes may have equal or similar work functions. For example, the work functions may be equal within a tolerance of +/?0.1 V. The memory cell can be arranged in various configurations including a FeFET (ferroelectric field effect transistor) and a FeRAM (ferroelectric random access memory). A set of memory cells can be arranged in a string such as a NAND string.

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

Abstract: A circuit comprising an input, a ground, a first switch, a second switch and a bi-polar memristor, wherein the first switch is a first transistor and a gate of the first transistor is connected to a line to instruct setting of the bi-polar memristor, and the second switch is a second transistor and a gate of the second transistor is connected to a line to instruct re-setting of the bi-polar memristor.

Abstract: A system and method for retrofitting an electric center irrigation pivot to have a standardized user interface and remote control functionality. A local control element having a standardized local user interface is installed at a pivoting point of the pivot by bypassing an existing control logic of an original control system while using an existing transformer of the original control system. A remote control element having a standardized remote user interface is also installed at the pivoting point of the pivot, and is functionally integrated with the local control element. A position-determining element is mounted on a movable portion of the electric pivot. Retrofitting multiple pivots provides each with the same standardized user interfaces. Because existing elements of the original control system are either bypassed or used, uninstalling the system and reverting to the original control system can be quickly and easily accomplished.

Abstract: The present technique relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor memory device having improved reliability includes an address decoder applying a program voltage to a selected word line coupled to selected memory cells, among the plurality of memory cells, and a read and write circuit applying a program permission voltage or a program inhibition voltage to bit lines coupled to the selected memory cells, and a control logic controlling the read and write circuit to sequentially apply the program permission voltage and the program inhibition voltage to the bit lines coupled to the selected memory cells when the program voltage is applied.

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.