Abstract: Data paths are provided to a memory array. The data paths include switches for selectively aligning the data paths to different multiplexors for reading or writing to the memory array. Read data lines are steered to selected sense amplifiers based on the decode address, using the switches. Write data lines are steered to selected write drivers based on the decode address, using the switches.

Abstract: A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower threshold voltages. A compensation pass bias can be reduced as the state being sensed at a selected word line increases to account for the different effects. A compensation pass bias for an adjacent word line may be reduced with the application of larger read reference voltages to a selected word line. Other variations to a compensation pass bias are provided.

Abstract: A resistive memory apparatus including a resistive memory cell array and a control unit is provided. The resistive memory cell array includes resistive memory cells. The control unit is configured to receive a logic data, determine a logic level of the logic data, and select one resistive memory cell from the resistive memory cells. The control unit provides a set signal or a reset signal to the selected resistive memory cell in a writing period according to the logic level of the logic data. The set signal includes a first set pulse and a second set pulse having a polarity opposite to that of the first set pulse. The reset signal includes a first reset pulse and a second reset pulse having a polarity opposite to that of the first reset pulse. A writing method of the resistive memory apparatus is also provided.

Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. In one aspect, read voltages are set and optimized based on a time period since a last sensing operation. A timing device such as an n-bit digital counter may be provided for each block of memory cells to track the time. The counter is set to all 1's when the device is powered on. When a sensing operation occurs, the counter is periodically incremented based on a clock. When a next read operation occurs, the value of the counter is cross-referenced to an optimal set of read voltage shifts. Each block of cells may have its own counter, where the counters are incremented using a local or global clock.

Abstract: Provided herein is a memory device including a plurality of memory blocks comprising a plurality of memory blocks each comprising a plurality of memory cells; a peripheral circuit coupled to the memory cells through bit lines, and suitable for sensing currents of the bit lines varying according to threshold voltages of the memory cells; and a control logic suitable for controlling the peripheral circuit so that the current amount of the bit lines vary during a program operation of the memory cells.

Abstract: A method of programming electrical fuses reliably is disclosed. If a programming current exceeds a critical current, disruptive mechanisms such as rupture, thermal runaway, decomposition, or melt, can be a dominant programming mechanism such that programming is not be very reliable. Advantageously, by controlled programming where programming current is maintained below the critical current, electromigration can be the sole programming mechanism and, as a result, programming can be deterministic and very reliable. In this method, fuses can be programmed in multiple shots with progressive resistance changes to determine a lower bound that all fuses can be programmed satisfactorily and an upper bound that at least one fuse can be determined failed. If programming within the lower and upper bounds, defects due to programming can be almost zero and, therefore, defects are essentially determined by pre-program defects.

Abstract: Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.

Abstract: An integrated circuit according to an embodiment includes: a plurality of first wiring lines; a plurality of second wiring lines intersecting with the plurality of first wiring lines; a plurality of resistive change memory elements provided in cross regions of the plurality of first and second wiring lines, each of which includes a first electrode connected to a corresponding first wiring line, a second electrode connected to a corresponding second wiring line, and a resistive change layer provided between the first and second electrodes, and in each of which a resistive state between the first electrode and the second electrode can be programmed from one of a first resistive state and a second resistive state, which has a larger resistance value than the first resistive state, to the other; and a driver driving the plurality of first and second wiring lines.

Abstract: A semiconductor device includes: first and second memory cell regions disposed adjacent to each other in a first direction, and suitable for sharing a sub-word line driving signal, and a first sub-word line driving unit disposed in a crossing area that is disposed between the first and second memory cell regions in a diagonal direction. The first sub-word line driving unit includes a first sub-word line driver for driving the first memory cell regions, a second sub-word line driver for driving the second memory cell regions, and an interconnection for transmitting the sub-word line driving signal, which extends in the first direction.

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.

Abstract: A circuit includes a first driver to provide a first driver signal at an output. The first driver signal corresponds to a voltage operatively coupled to a VSS terminal of the first driver when driving a logic low. A first capacitor includes a first terminal coupled to the VSS terminal of the first driver. A boost circuit includes a first input coupled to the output of the first driver and a first output coupled to a second terminal of the first capacitor. The boost circuit is configured to cause the first capacitor to provide a boosted voltage at the VSS terminal.

Abstract: A memory control circuit unit, a memory storage device and a reference voltage generation method are provided. The method comprises: detecting a first impedance characteristic of a memory controller via a first connection interface of a memory interface and detecting a second impedance characteristic of a volatile memory via a second connection interface of the memory interface; generating an internal reference voltage according to a detection result; and resolving data signal received by the memory interface according to the internal reference voltage. Therefore, an influence on the internal reference voltage owing to the manufacture deviation of impedance element of the memory controller and/or the volatile memory can be reduced.

Abstract: A resistive memory device resistive memory device includes a bit line configured to be driven by a bit line driver, a source line configured to be driven by a source line driver adjacent to the bit line driver, and a plurality of memory cells connected between the bit line and the source line. An electrical path of the bit line from each of the plurality of memory cells to the bit line driver increases as an electrical path of the source line from each of the plurality of memory cells to the source line driver decreases.

Abstract: Methods of operating a die, including counting primary clock cycles of a clock signal in a counter, monitoring a signal indicative of high current demand during secondary clock cycles of the clock signal, determining a total unit consumption of current responsive to a particular value of the signal indicative of high current demand during the secondary clock cycles of the clock signal, and pausing an access operation for the die at a designated point. When a value of the counter matches an assigned counter value of the die while the access operation is paused, determining whether a value of the total unit consumption of current exceeds a unit limit, and resuming the access operation and resetting the value of the total unit consumption of current if the value of the total unit consumption of current is less than or equal to the unit limit.

Abstract: A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.

Abstract: Aspects of a continuous-time memory cell circuit are described. In various embodiments, the memory cell circuit may comprise a memory cell, a current source coupled to the memory cell, and circuitry for programming the memory cell at an adaptive rate, based on a target voltage for programming, using a feedback loop between a gate terminal of the memory cell and a reference control input. Based on the circuitry for programming, the memory cell may be programmed according to various voltage and/or current references, by linear injection and/or tunneling mechanisms. According to various aspects, the circuitry for programming drives a memory cell to converge to a voltage target for programming within a short period of time and to a suitable level of accuracy.

Abstract: A semiconductor circuit may include a control circuit configured to generate a second start signal and a plurality of serialization control signals by synchronizing a first start signal with first and second clock signals.

Abstract: In response to a request to read data, the non-volatile memory system identifies the physical block that is storing the requested data. Read parameters associated with the physical block are also identified. The read parameters include bit error rate information. The memory system chooses whether to use a read process with a faster sense time or a read process with a slower sense time based on the bit error rate information and temperature data. The requested data is read from the identified physical block using the chosen read process configured by at least a subset of the read parameters.

Abstract: One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.