Abstract: According to example embodiments of inventive concepts, a nonvolatile memory device includes a memory cell array, an address decoder, an input/output circuit, a voltage generation circuit, and control logic. The memory cell array includes a plurality of memory blocks on a substrate. Each of the memory blocks includes a plurality of strings connected between bit lines and a common source line. The address decoder is configured to measure impedance information of word lines of a selected memory block. The voltage generation circuit is configured to generate word line voltages to be applied to word lines, and at least one of the word line voltages includes an offset voltage and a target voltage. The control logic is configured to adjust a level of the offset voltage and the offset time depending on the measured impedance information of the word lines.

Abstract: A flash memory system for use in an electronic system comprising an integrated circuit such as a microcontroller. The flash memory system embodies one or more circuits adapted to operate at sub- or near-threshold voltage levels. These low-power circuits are selectively activated or de-activated to balance power dissipation with the response time of the memory system required in particular applications.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a resistance-change element having first and second terminals, a transistor having third and fourth terminals and a control terminal, the third terminal being electrically connected to the second terminal, and a driver electrically connected to the first and fourth terminals, applying one of a first potential and a second potential to the first terminal and the other of the first and second potentials to the fourth terminal in writing, and applying one of the first and second potentials to the first terminal and the other of the first and second potentials to the fourth terminal in reading.

Abstract: Embodiments relate to systems, methods and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus comprising a first resistor connected to a first receiver input, four N-type metal oxide semiconductor (NMOS) field effect transistors (FETs), two PMOS FETS, and a trans-impedance amplifier wherein an input terminal of the trans-impedance amplifier is connected to a drain terminal of the second NMOS FET. Additional embodiments including other circuitry, associated methods, and media comprising instructions associated with generation of circuit design files are also described.

Abstract: Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode.

Abstract: The control unit performs a first writing operation to obtain a first threshold voltage distribution, and a second writing operation to obtain a second threshold voltage distribution lower than the first threshold voltage distribution, and a third threshold voltage distribution higher than the first threshold voltage distribution. A verify reading operation is performed to determine whether any of the first to third threshold voltage distributions has been obtained. A step-up writing operation, in accordance with a result of the verify reading operation, increases a program voltage by a predetermined step-up width. The step-up writing operation, after start of the second writing operation, sets the step-up width to a first step-up width, and when the second writing operation has reached a predetermined phase, changes a second step-up width greater than the first step-up width at least once.

Abstract: Provided are a weighting device that may be driven at a low voltage and is capable of embodying multi-level weights, a neural network, and a method of operating the weighting device. The weighting device includes a switching layer that may switch between a high resistance state and a low resistance state based on a voltage applied thereto and a charge trap material layer that traps or discharges charges according to a resistance state of the switching layer. The weighting device may be used for controlling a weight in a neural network.

Abstract: Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access transistors, and optionally a separate read port. The cross-coupled inverters in each memory cell may have a positive power supply terminal. The positive power supply terminal of each memory cell along a given column in the array may be coupled to a corresponding pull-up transistor. The pull-up transistor may receive a control signal from a pull-up weakening control circuit. The control signal may be temporarily elevated during write operations and may otherwise be driven back down to ground to help optimize read performance. The pull-up weakening control circuit may be implemented using a chain of n-channel transistors or a resistor chain.

Abstract: A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

Abstract: A memory (1205) is disclosed. The memory (1205) can includes a stack of dynamic Random Access Memory (DRAM) cores (1210, 1215, 1220, 1225) in a three-dimensional stacked memory architecture (1230). Each of the DRAM cores (1210, 1215, 1220, 1225) can include a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data. The memory (1205) can also include logic layer (1235) which can include an interface (1305) to connect the memory (1205) with a processor (120). The logic layer (1235) can also include a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4) and a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

Abstract: A memory device capable of narrowing the threshold voltage distribution thereof includes word lines, bit lines, memory cells, a word line driver configured to apply voltage to a selected word line, a sense amplifier circuit configured to detect data of the memory cell, and a controller configured to control the word line driver and the sense amplifier. A write sequence includes a write operation in which write voltage is applied to the selected word line by the word line driver, and a verify operation in which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing to the selected memory cell is completed. Based on second data that is written later than the first data to an adjacent memory cell adjacent to the selected memory cell, the controller changes the reference voltage used for completing the writing to the selected memory cell.

Abstract: An OTP (One-Time Programmable) memory including OTP memory cells that utilize OTP elements fabricated in CMOS FinFET processes. The OTP memory cell can also include at least one selector built upon at least one fin structure that has at least one CMOS gate to divide the fin structure into at least a first and a second active region. The selector can be implemented as a MOS device, dummy-gate diode, or Schottky diode as selector such as by using different types of source/drain implants. The OTP element that can be implemented as polysilicon, silicided polysilicon, CMOS metal gate, any layers of metal as interconnect, or active region. In one embodiment, the OTP element can be a fin structure and can be built upon the same fin structure as the at least one of the selector. By using different source/drain implant schemes on the two active regions, the selector can be turned on as MOS device, MOS device and/or diode, dummy-gate diode, or Schottky diode.

Abstract: Embodiments are provided that include a method including providing a first voltage to a memory cell prior to an operation, wherein a magnitude of the first voltage is approximately 5 volts. The method further includes providing a second voltage to the memory cell during the operation, wherein a magnitude of the second voltage is in the range of approximately 1.0 and 1.5 volts. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.

Abstract: A memory system includes first through fifth pins connectable to a host device to output to the host device a first signal through the third pin and to receive from the host device a first chip select signal through the first pin, a second chip select signal through the second pin, a second signal through the fourth pin, and a clock signal through the fifth pin, an interface circuit configured to recognize, as a command, the second signal received through the fourth pin immediately after detecting the first or second chip select signal, and first and second memory cell arrays. The interface circuit and the first and second memory cell arrays are provided in one common package, and is configured to access the first memory cell array when detecting the first chip select signal, and to access the second memory cell array when detecting the second chip select signal.

Abstract: A memory including at least one line to which memory cells are coupled. A control circuit is configured to emit an end-of-operation signal at the end of the execution of an operation on at least one memory cell, and a glitch detection circuit coupled to the memory line is configured to supply a glitch detection signal when a falling edge of the amplitude of a voltage signal appears on the memory line in the absence of the end-of-operation signal.

Abstract: A semiconductor memory device includes: a cell array region storing and outputting data selected based on an input address and including a first cell region storing a failure address; an input control signal generator generating a compression signal informing presence of failure cells, and generating an input control signal based on the compression signal; an output control signal generator generating an output control signal in response to the input control signal and a pre-charge signal; a failure address latch storing the input address as the failure address in response to the input control signal, and outputting the failure address based on the output control signal; a failure address mapper mapping the failure address to the data line to store the failure address in the first cell region; and a non-volatile memory device receiving the failure address from the first cell region and programming it in a rupture mode.

Abstract: According to one embodiment, a memory device includes a spin transfer torque magnetoresistive element including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, a temperature detecting unit detecting an ambient temperature of the magnetoresistive element, and a write voltage generating unit generating a write voltage for the magnetoresistive element in accordance with the temperature detected by the temperature detecting unit.

Abstract: Some embodiments include apparatuses and methods using first and second select gates coupled in series between a conductive line and a first memory cell string of a memory device, and third and fourth select gates coupled in series between the conductive line and a second memory cell string of the memory device. The memory device can include first, second, third, and fourth select lines to provide first, second, third, and fourth voltages, respectively, to the first, second, third, and fourth select gates, respectively, during an operation of the memory device. The first and second voltages can have a same value. The third and fourth voltages can have different values.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell array including a first memory cell having a variable resistive element, a second memory cell array including a second memory cell having the variable resistive element, a reference signal generation circuit which generates a reference signal, a sense amplifier having a first input terminal and a second input terminal, and a read enable control circuit which generates a read enable signal in accordance with a command from outside and control switching between a single cell read mode and a twin cell read mode.