Abstract: PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1?xCa2+xMnO thin film composition, where 0.1<x<0.6; in response to the selection of x, varying the ratio of Mn and O ions as follows: O2?(3±20%); Mn3+((1?x)±20%); and, Mn4+(x±20%). When the PCMO thin film has a Pr3+0.70Ca2+0.30Mn3+0.78Mn4+0.22O2?2.96 composition, the ratio of Mn and O ions varies as follows: O2?(2.96); Mn3+((1?x)+8%); and, Mn4+(x?8%). In another aspect, the method creates a density in the PCMO film, responsive to the crystallographic orientation. For example, if the PCMO film has a (110) orientation, a density is created in the range of 5 to 6.76 Mn atoms per 100 ?2 in a plane perpendicular to the (110) orientation.

Abstract: A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. A semiconductor package fabricated using the lead frame and a fabrication method for the semiconductor package are also disclosed.

Abstract: A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a ballout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired ballout footprint.

Abstract: A source electrode, a gate electrode, and a drain electrode formed on a front face active region of a semiconductor substrate in a shape of teeth of a comb are covered with an insulating film such as polyimede etc., as well as all of the upper surface and the side surfaces of the insulating film are covered with a metal protective film. Via hole receiving pads connected to the source electrode, the gate electrode, and the drain electrode are respectively connected to bonding pads on a reveres face of the semiconductor substrate through via holes.

Abstract: A manufacturing method for an in-plane switching mode liquid crystal display (LCD) unit is provided. The method includes steps of: providing a substrate, forming a first conductive layer on the substrate, patterning the first conductive layer to form a gate line, a comb-shaped first electrode, a wiring pad, and a comb-shaped second electrode by a first photo etching process, forming a first insulation layer and a first semi-conductive layer, patterning the first insulation layer and the first semi-conductive layer to form a channel, an insulation structure, a dielectric layer, and plural crossed-conductive line insulation structures by a second photo etching process, forming a second semi-conductive layer and a second conductive layer on the substrate, patterning the second semi-conductive layer and the second conductive layer to form a source/drain electrode, a data line, a connecting electrode, and a first electrode by a third photo etching process, and forming a passivation layer.

Abstract: A method of forming a capacitor is disclosed. The method includes forming a first substrate layer, and forming a first electrode on the first substrate layer. The first electrode includes at least one non-smooth surface and is formed from a material selected from the group consisting of transition metals, conductive oxides, alloys thereof, and combinations thereof. The method also includes forming a dielectric on the first electrode and the first substrate layer, and forming a second electrode on the dielectric and the first substrate layer. The second electrode includes at least one non-smooth surface. The method further includes forming a second substrate layer on the second electrode.

Abstract: Methods of forming power semiconductor devices include forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate. A gate electrode is formed on the first surface. Base and base shielding region dopants are implanted into the transition region using the gate electrode as an implant mask. A plurality of annealing steps are performed so that the base shielding region dopants are driven in laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the transition region to a minimum width.

Abstract: A semiconductor component includes a semiconductor die, and an on board capacitor on the die for filtering transient voltages, spurious signals and power supply noise in signals transmitted to the die. The capacitor includes a first electrode in electrical communication with a first terminal contact for the component, and a second electrode in electrical communication with a second terminal contact for the component. The electrodes are separated by a dielectric layer and protected by an outer protective layer of the component. The capacitor can be fabricated using redistribution layers on a wafer containing multiple dice. The component can be used to construct systems such as multi chip packages and multi chip modules.

Abstract: In a method for manufacturing a semiconductor device, a gate insulating film and a gate electrode are first formed on a substrate. Next, Ge ions, Si ions, or the like are implanted to make the surface of the substrate amorphous, using the gate electrode as a mask. Thereafter, impurities such as B ions or the like, for forming a doped region, are implanted into the amorphous area of the substrate, using the gate electrode as a mask. Furthermore, the doped region is irradiated with visible light for a short period of time.

Abstract: The invention provides a method of manufacturing a semiconductor that improves the productivity and the yield of a product, and grinds a semiconductor substrate so that it has almost uniform thickness. The method can include forming a protrusion on a semiconductor substrate having a first area and a second area surrounding the first area. The protrusion protruding above first area. A support being disposed on a surface on which the protrusion is formed, of the semiconductor substrate so that a through hole of the support overlaps with the first area. The semiconductor substrate can be grinded from a surface opposite to the surface on which the protrusion is formed.

Abstract: A semiconductor storage device includes a voltage supply circuit generating a voltage of 5V, a voltage polarity inversion circuit generating a voltage of ?5V, a select-and-connect circuit supplying the voltages of 5V and ?5V to a memory cell array, a 5 V voltage level detection circuit detecting the voltage derived from the voltage supply circuit, and a ?5 V voltage level detection circuit detecting the voltage derived from the voltage polarity inversion circuit. Absolute values of the voltages detected by the voltage level detection circuits are lower than ever before. This allows a gate insulation film to be thinner. A memory-function film is formed on both sides of a gate electrode in the semiconductor storage device. This also make the gate insulation film thinner. The thin gate insulation film suppresses the short-channel effect, so that each memory element of the memory cell array is miniaturized.

Abstract: A manufacturing method of a circuit substrate, in which an electronic circuit is formed on a surface of a base member by a solution jetting device. The manufacturing method comprises: jetting liquid drops of a solution which is supplied into a nozzle having a discharge port with an inner diameter of 0.1 ?m to 100 ?m and includes a plurality of fine particles to form an electronic circuit by melting and sticking to one another and a dispersant for dispersing the fine particles, from the discharge port toward the surface of the base member by applying a voltage of an arbitrary waveform to the solution to charge the solution; and exposing the jetted liquid drops received on the surface of the base member to light or heat to make the fine particles melt and stick to one another.

Abstract: The active region of a long-wavelength light emitting device is made by providing an organometallic vapor phase epitaxy (OMVPE) reactor, placing a substrate wafer capable of supporting growth of indium gallium arsenide nitride in the reactor, supplying a Group III–V precursor mixture comprising an arsenic precursor, a nitrogen precursor, a gallium precursor, an indium precursor and a carrier gas to the reactor and pressurizing the reactor to a sub-atmospheric elevated growth pressure no higher than that at which a layer of indium gallium arsenide layer having a nitrogen fraction commensurate with light emission at a wavelength longer than 1.2 ?m is deposited over the substrate wafer.

Abstract: In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the dielectric coupling between the trench electrode (11) and the body portion at the bottom (27) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.

Abstract: A semiconductor memory device and fabrication method of same includes the processes of forming sacrifice gates on a silicon substrate with the sacrifice gates apart from each other. A first conductive layer is formed on an exposed portion of the silicon substrate between the sacrifice gates and a first inter-insulation layer is formed that exposes the first conductive layer and the sacrifice gates. The exposed sacrifice gates are removed to form openings and damascene gates are subsequently formed in the openings. Capping layers are formed on the top of the gates and a second conductive layer is formed on the exposed first conductive layer. A second inter-insulation layer is formed on the silicon substrate, and bit line contacts that expose the second conductive layer are formed by etching the second inter-insulation layer.

Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a semiconductor layer. A field-effect transistor gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel having the appropriate conductivity type.

Abstract: A thin layer comprising at least a metal and a non-metallic chemical element is deposited on an oxidized layer of a substrate arranged in a reactor. The thin layer is formed by a plurality of superposed atomic layers formed by repetition of a reaction cycle comprising at least a first step of injecting a first halogenated metallic reagent into the reactor, a first reactor purging step, a second step of injecting a second reagent comprising the non-metallic chemical element into the reactor and a second reactor purging step. The process comprises, after each deposition of an atomic layer, at least one densification sequence of the atomic layer comprising a third purging step, an additional injection step of the second reagent and a fourth purging step. The time length of a densification sequence is substantially longer than the time length of a reaction cycle.

Abstract: Methods for manufacturing semiconductor devices are disclosed. In a disclosed method, a first nitride layer and a device isolation oxide layer are etched to thereby expose a portion of a silicon substrate where an active region is to be formed. An epitaxial growth is performed on the active region and a first oxide layer is deposited thereon. Portions of the first oxide layer where a source and a drain are to be formed are etched. The first oxide layer deposited on the portions where the source and the drain are to be formed is then etched. An epitaxial growth is performed on the portions where the source and the drain are to be formed to thereby form the source and the drain. A second nitride layer is deposited thereon. A portion of the first oxide layer located where a gate is to be formed is etched using a gate mask. A third nitride layer is deposited on the source, the drain, and the exposed active region and then etched back to thereby form a nitride layer to control a length of the gate.

Abstract: A p-GaN layer 5 comprising materials such as a Group III nitride compound semiconductor is formed on a sapphire substrate 1 through MOVPE treatment, and a first metal layer 6 made of Co/Au is formed thereon. Then in a planar electron beam irradiation apparatus using plasma, electron beams are irradiated to the p-GaN layer 5 through the first metal layer 6. Accordingly, the first metal layer 6 prevents the surface of the p-GaN layer 5 from being damaged and resistivity of the p-GaN layer 5 can be lowered. Next, a second metal (Ni) layer 10 is formed on the first metal layer 6. And the first metal layer 6 is etched through the second metal layer 10 by using fluoric nitric acid. As a result, the first metal layer is almost completely removed. Then a light-transmitting p-electrode 7 made of Co/Au is formed thereon. As a result, a p-type semiconductor having decreased contact resistance and lower driving voltage can be obtained and optical transmittance factor of the p-type semiconductor improves.