Abstract: A thin film SOI CMOS device wherein the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.

Abstract: A manufacturing method of a semiconductor device of the present invention comprises a first step of exposing a periphery of a first region of a photoresist layer coating an insulating layer formed on a semiconductor substrate and a periphery of a second region for positioning, and a second step of heating said photoresist layer in ammonia atmosphere and forming an alkali insoluble portion in the periphery of the first region and that of the second region, a third step of exposing a third region, which is smaller than the first region, and the second region and developing these regions, a fourth step of etching the third region and the second region to a predetermined depth, and a fifth step of repeating the third and fourth steps once or more in a region, which is smaller than the third region, and the second region.