Abstract: A method of fabricating heterojunction structures includes providing a semiconductor substrate and forming a plurality of semiconductor layers thereon. Ohmic and gate contacts are then formed on the plurality of semiconductor layers and portions of at least one of the semiconductor layers disposed between the ohmic and gate contacts are removed. Gate metal is then formed on the gate contacts. Source and drain regions are formed in the semiconductor layers and the formation is self-aligned to the gate metal. Following the formation of the source and drain regions, ohmic metal is formed on the ohmic contacts.

Abstract: A semiconductor device such as a Schottky-barrier rectifier diode is disclosed which has a barrier electrode formed on a semiconductor substrate of gallium arsenide or the like. Formed around the barrier electrode is an annular resistive layer, typically of titanium oxide, creating a Schottky barrier at its interface with the semiconductor substrate. The resistive layer has a sheet resistance of more than 10 kilohms per square. In order to prevent preliminary breakdowns from taking place at the peripheral part of the resistive layer before final breakdown of the device, the sheet resistance of the resistive layer is made higher as it extends away from the barrier electrode. For the ease of manufacture, the resistive layer can be divided into two or more annular regions of distinctly different sheet resistances.

Abstract: A first semiconductor layer, a second semiconductor layer for source and drain regions, and a bottom SiN layer are successively formed. After the bottom SiN layer is selectively etched to make an opening, a SiON layer and a top SiN layer are formed thereon. A resist pattern having an opening that is closer to the source region than to the drain region is formed on the top SiN layer. The top SiN layer and SiON layer are etched with the resist pattern used as a mask, to expose the second semiconductor layer. The SiON layer is side-etched with hydrofluoric acid until exposing the gate-side portion of the source-side bottom SiN layer. Then, the second semiconductor layer is etched to expose the first semiconductor layer and to form the source and drain regions, where the gate-side edge of the source region is determined by that of the source-side bottom SiN layer and the gate-side edge of the drain region is determined by that of the drain-side SiON layer.

Abstract: High mobility thin film transistors for fabricating integrated drivers for active matrix displays and a special method of fabrication for obtaining the thin film transistors having mobility sufficiently high enough as drivers operable in the several megahertz frequency range needed for driving high resolution active matrix displays.

Abstract: A method of producing an improved field effect transistor integrated circuit device in a semiconductor substrate embodying a first type dopant and having a recessed gate electrode and self-aligned source and drain regions can be made. A first masking layer is formed on the surface of said semiconductor substrate that is capable of masking the underlying silicon against oxidation. Portions of first masking layer is removed to form openings that at least define the gate electrode regions. The resultant exposed silicon area are oxidized to produce a thick sunken silicon oxide layer. The first masking layer is removed. A second opposite type dopant is introduced into the substrate on opposite sides of the sunken thick oxide layer that defines the region of the gate electrode to form source and drain regions. The sunken thick oxide layer is selectively removed, thereby forming a depression in the substrate that defines the gate region.

Abstract: A process of manufacturing a Bi-CMOS type semiconductor integrated circuit according to the present invention by to providing an isolation procedure wherein PMOS and NMOS transistor isolation areas are selectively oxidixed so as to form a second isolation oxide film, simultaneous with the selective oxidation of the polysilicon layer deposited on the bipolar transistor area after the semiconductor substrate in the bipolar transistor isolation area, which has been removed to a required thickness and selectively oxidized so as to form a thick first isolation oxide film for the bipolar transistor.

Abstract: A novel display screen structure and method of manufacturing such screens for use, for example, in large screen television displays. The process of the present invention is one which can be accomplished with no new materials, no critical geometric requirements such as critical separations and alignments and only low voltage drivers. The combination of these features results in a technology which can be easily scaled to large sizes to provide relatively low-cost large screens for televisions. An important step in the disclosed embodiment of the present invention is the alignment of a large plurality of columnar-shaped light emitting diode slivers in an uncured optical epoxy by applying an electric field through a mixture of such slivers and epoxy and then curing the epoxy to effectively fix the light emitting diode slivers in that aligned configuration.

Abstract: A rod base material for forming wafers for electronic devices is formed from a plurality of rod members made of selected materials. The rods are assembled in parallel and are bonded with each other into an integrated body. In one aspect of this invention, a mirror-finished bonding face is formed at the outer surface of each of the rod members, and is cleaned by a surface treatment using chemicals. Subsequently, respective rod members are assembled in parallel and brought into contact with each other at their respective bonding faces. The thus prepared and assembled rod members are maintained in a heated atmosphere until they combine into an integrated body to provide the base material. The rod base material is thereafter subjected to slicing to provide wafers used for forming electronic devices.

Abstract: To create bipolar and MOS transistors, a substrate is covered with polysilicon. The polysilicon is patterned to form gate electrodes in MOS transistor regions, and to form polysilicon patterns surrounding central openings in bipolar transistor base-and-emitter regions. Lightly-doped source and drain layers are created by implanting impurities into the MOS transistor regions, using the gate electrodes as masks. Active bases are formed in the base-and-emitter regions below the central openings. Then sidewalls are added to the polysilicon, narrowing the central openings and widening the gate electrodes. Impurities are implanted into the MOS transistor regions, using the widened gate electrodes as masks, to create heavily-doped source and drain layers. The active base areas are doped below the narrowed central openings to create emitters.

Abstract: A stacked semiconductor structure including a base structure (18/19) is comprised of a semiconductor substrate having active regions (21) of devices (N1, . . . ) formed therein and/or a plurality of polysilicon lines (23-1, . . . ) formed thereupon; a first thick passivating layer (26/27) having a set of first metal contact studs (30-1, . . . ) therein contacting at least one of said active regions (21) and/or said polysilicon lines (23-1, . . . ), the surface of said first metal contact studs being coplanar with the surface of said first thick passivating layer; a plurality of first polysilicon lands (31-1, . . .

Abstract: A silicon substrate (20) having a pnpn structure is soldered to a metal plate (10). A silicon oxide film (16) is naturally formed on the side surface of the silicon substrate during a process of removing defective part of the side surface, and a metal component penetrates into the silicon oxide film. The silicon substrate is dipped into an etchant to etch the silicon oxide film, so that a leak current through the metal component is effectively prevented.

Abstract: A method of fabricating a high-density multilayer copper/polyimide interconnect structure utilizing a blanket tantalum/tantalum oxide layer that electrically connects all of the electroplating seed layers to the edge of the substrate; upon completion of the electroplating process, the excess tantalum/tantalum oxide layer is etched off to produce isolated conductor lines. A multilayer copper/polyimide interconnect structure may be fabricated by repeating this fabrication sequence for each layer.

Abstract: A metal pin grid array package and a process for the assembly of the package is provided. The package includes a metal or metal alloy base component having an ordered array of holes. Terminal pins are electrically interconnected to a desired circuit and extend through the ordered array of holes. A dielectric polymer sealant bonds a cover component to both the circuit and to the base component. During package assembly, the polymer sealant flows into the holes comprising the ordered array of holes electrically isolating the terminal pins from the base component.

Abstract: A method is described for selectively masking sidewall regions of a concave surface formed in a semiconductor body, the method comprising the steps of: forming a conformal layer of masking material on a sidewall of the concave structure; emplacing in the concave structure, a selectively removable material that partially fills the concave structure, an upper surface of the material determining the edge of a region of the concave structure to be masked; removing a portion of the conformal layer above the upper surface of the selectively removable material; and removing the selectively removable material to leave a region of remaining conformal material as a mask.

Abstract: A lead frame includes a die pad for mounting thereon a semiconductor chip having a plurality of electrodes, a plurality of leads for electrical connection with the plurality of electrodes of the semiconductor chip, an outer frame disposed on the periphery of the die pad for supporting the die pad and the plurality of leads, and a resin guide portion extending to the vicinity of the die pad from the outer frame for guiding a molten resin over and under the semiconductor chip during resin packaging. A semiconductor device manufacturing method includes mounting a semiconductor chip having electrodes on a substrate having a resin guiding portion for guiding a resin over and under the semiconductor chip during resin packaging; electrically connecting leads on the substrate to the electrodes positioning the semiconductor chip and the substrate between a pair of mold halves injecting a molten resin into the mold and solidifying the resin.

Abstract: A lead frame includes an outside frame portion having an central opening, and a rectangular mount portion supported by the outside frame portion and disposed within the central opening, and on which an electronic element is adapted to be mounted. The lead frame also includes at least one lead element array disposed along a side of the mount portion, respectively, the lead elements included in the array being connected to each other by a common tie bar element, and at least two expandable tie bar elements extending between the outside frame portion and each of the lead element arrays to support each lead element array by the outside frame portion, each of the expandable tie bar elements including a shaped portion which can be expanded by a deformation thereof. In a method of producing an electronic component using the lead frame, a process of bending the lead elements is performed before an electrolytic-plating process thereof.

Abstract: A surface layer (10), for example oxide, is provided on a first major surface (2) of a semiconductor body (1). A masking layer (11) having at least one window (12) is defined on the surface layer (10). The surface layer (10) and the semiconductor body (1) are etched through the window (12) to define an opening (13in the surface layer (10) and a recess (14) within the semiconductor body (1) extending beneath the surface layer (10) so that a rim portion (10a) of the surface layer (10) overhangs the recess (14). The rim portion (10a) of the surface layer (10) is removed by causing a settable flowable material (15) to flow onto the surface layer (10) and into the recess (14) and then causing the flowable material to set and thereby change volume to apply a force for causing the rim portion (10a) to break away from the remainder ( 10b) of the surface layer (10). The set flowable material (150) and thus the rim portion (10a) of the surface layer (10) are then removed.

Abstract: A semiconductor device comprising three recessed portions formed at a very small pitch on the surface of a semiconductor substrate, remaining regions formed between these recessed portions as impurity diffused regions serving as the source and the drain, respectively, and a conductive region as a gate electrode formed through an insulating film within the central recessed portion, and a method of manufacturing such a semiconductor device are disclosed. With this device, its gate length can be made shorter than that in the prior art and the junction leakage is reduced, resulting in miniaturization and an improvement in the characteristics.

Abstract: A high voltage junction is formed in a dielectrically isolated island by forming a second conductivity type region in a first conductivity type island wherein the second conductivity type region extends to and between a pair of opposed dielectric isolation wall. This shafts the boundaries to the dielectric walls and removes the low breakdown regions.

Abstract: The present invention provides a process which is particularly suited for mass-producing solid electrolytic capacitors. The process utilizes a combination of a mold and a presser member. The mold has a series of molding recesses, and a lead receiving groove extending along and through the series of molding recesses. The presser member has a corresponding series of pressing projections. A portion of a continuous lead wire is placed in the groove, and powdered electrode material is loaded in the molding recesses. The presser member is then moved toward the mold, so that the powdered material is compacted within the molding recesses by the pressing projections. The resulting compacts are removed from the mold together with the wire. The same process steps are repeated with respect to other portions of the wire.