Abstract: A novel semiconductor laser device includes a P-type semiconductor substrate, an N-type InP current blocking layer on the substrate, a P-type InP buried layer of which has the same thickness as and is surrounded by the first current blocking layer, and a ridge, on the buried layer, having a double heterojunction structure therein and including a stack of a planar P-type first InP cladding layer, a planar InGaAsP active layer, and a planar N-type second InP cladding layer. The ridge has a width of the same order as that of the buried layer. A P-type InP current blocking layer is disposed on the N-type current blocking layer burying the ridge and an N-type contact layer is formed opposite and in contact with the P-type current blocking layer and the N-type cladding layer. The conductivity types of the layers can be reversed.

Abstract: Methods are disclosed for making semiconductor windows which are transparent to light in the infrared range which have good electrical conductivity and are formed of a substrate material (11) having a semiconductor coating (14) having a dopant included therein. The coating is diffused, grown or deposited on one surface of the substrate and is controlled to obtain both low electrical resistivity and high infrared transmissivity. The coating can be formed of the same material as the substrate or can be a different material. Windows having particular thermal properties are formed utilizing zinc selenide and zinc sulfide as the substrate.

Abstract: A method for fabricating a semiconductor device comprises the steps of forming an insulating layer by the CVD method on a main surface of a semiconductor substrate, fluidizing the insulating layer by heat treatment, unifying a thickness of the insulating layer, opening contact holes in desired points of the insulating layer, and forming conductor contacts for interconnection on the contact holes. The insulating layer is has a uniform thickness in any area on the semiconductor device, so that over-etching of the insulating layer in opening contact holes can be prevented, and the step coverage is well improved.

Abstract: A structure and method of fabricating a active matrix display with halftone grayscale and wide viewing angle, having an active matrix array and a control capacitor array fabricated on separate substrates.

Abstract: A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material.

Abstract: A base-coupled logic gate is characterized by input Schottky diodes that are directly formed on the base region of the switching transistor for the gate. A logic of this type provides flexible circuit arrangements and savings in required area, while achieving very high speeds. As a result of the savings in area, the buried layer capacitance of the gate is also reduced, which facilitates the high-speed operation of the circuit.

Abstract: A process for fabricating an isolated silicon on insulator (SOI) field effect transistor (FET) (10, 11, 13, 15). The SOI FET is made on a substrate material (12). In one form, a first control electrode referred to as gate (24), is contained within the substrate (12) underlying a dielectric layer (14). A second control electrode referred to as gate (26) overlies a dielectric layer (28). A source and a drain current electrode are formed from a germanium-silicon layer (18). A silicon layer (16) forms an isolated channel region of the SOI FET. The gates (12, 24) are separated from the channel by gate dielectric layers (14, 28). The germanium-silicon layer (18) is much thicker than the silicon layer (16) which is made thin to provide a thin channel region. An optional nitride layer 20 overlies the germanium-silicon layer (18).

Abstract: In some circuitry, field effect transistors are produced by employing polycrystalline conductive regions including the channel and connections to the source and drain. Conventional methods for producing such transistors involve depositing a thin polycrystalline channel region, patterning this region overlying the patterned region with an insulator, producing openings in the insulator for contacts to source and drain, and depositing a thick polycrystalline contact region. Processing complexity is, however, substantially reduced by first forming interconnect areas, source region and drain regions; then opening a region for the channel; and finally depositing a layer to form the channel. Thus, at least three processing steps are eliminated and vertical dimensions are reduced.

Abstract: A gettering site is formed on the backside of a wafer, contaminant impurities are trapped in the gettering site by heat treatment, a contaminated layer of the gettering site including the impurities is removed. The impurities are thus prevented from being freed from the gettering site into the wafer. A new gettering site is then formed on the backside of the wafer. Such a gettering operation has therefore a refresh function.

Abstract: A sputter-etch process is used to etch vias having substantially vertical sidewalls, such that a sloped sidewall is formed. Using a silicon dioxide layer in which to form the vias, slopes of approximately 45.degree. may be obtained. A second insulator layer may be provided to protect the leads and other portions of the device during the sputter-etch to prevent damage.

Abstract: A field effect transistor having regions (20, 20', and 20") which respectively function as a planar elevated surface for gate, drain, and source electrical contact, and method of fabrication. The transistor overlies a substrate (12) and is formed partially from active areas (14 and 14'). The regions (20, 20', and 20"), each underlie or are surrounded by a dielectric layer (22). A gate is formed by a gate layer (24). A source (30) is formed within region (20") and is electrically connected to active area (14'). A drain (30') and channel region are formed within region (20'). Electrical contact is made to the source (30), drain (30') and gate layer (24) by conductive layers (34", 34', and 34, respectively).

Abstract: The present invention introduces a method to fabricate an active PMOS thin film transistor (or p-ch TFT) having an epitaxially grown channel region for high performance operation characteristics. Typically this p-ch TFT device would be fabricated overlying an NMOS active device, thereby becoming an active load (or pullup) to an NMOS device used is such applications as creating a memory cell in static random access memories (SRAMs). Conductivity types (p-type or n-type) may be interchanged to construct an n-ch TFT coupled with a PMOS active device if so desired. The fabrication of the TFT of the present invention may be used to form a CMOS inverter or simply an active pullup device when integrated into conventional CMOS fabrication processes.

Abstract: A process for forming a thin film field effect transistor, particularly adapted for use in SDRAM devices using CMOS flip-flop circuits, wherein the transistor has a drain-channel P-N junction that is precisely spaced from the gate electrode, the process involving the etch back of the edge of the gate electrode, either prior to ion implantation to form the source and drain, or following the implantation.

Abstract: A method for manufacturing a semiconductor apparatus, providing steps of (i) laminating a first polysilicon layer on the whole surface of a semiconductor substrate through a first oxide layer, (ii) removing the first polysilicon layer and first oxide layer in an element separation region so as to form a trench therein and to treat the residual first polysilicon layer and first oxide layer as a bottom gate electrode and an insulating film respectively, (iii) forming a monocrystalline silicon layer by epitaxial growth on the whole surface of the semiconductor substrate including the trenches, (iv) removing the monocrystalline silicon layer in the element separation region, laminating a second oxide layer on the whole surface of the semiconductor substrate including the removing portion, and making the second oxide layer remain as an element separation film in only the element separation region, and (v) forming a gate oxide film and a top gate electrode on the residual monocrystalline silicon film, and forming a

Abstract: A process for the manufacture of power-MOS semiconductor devices achieves high cell density by the use of self-aligning techniques and photographic exposure equipment of the stepper type. The process calls for definition and formation of the source by a complementary spacer technique and metallization of the source and gate contact areas by silicides after formation of spacers on the gate wall.

Abstract: Batch assembly methods for high density packaging of power semiconductor chips in hermetic thin packagings includes providing silicon chip arrays with thermocompressively bonded foil contacts, preparing ceramic lid arrays which contain upper surface and lower margin direct-bonded copper coverings and through-the-lid high current spherical conductors, coining Cu/Mo/Cu or copper cup arrays, die mounting within each respective cup a respective semiconductor chip, superpositionally registering a lid array with a strip form of cup array, and solder reflowing to hermetically seal all hermetic thin packagings within a registered set of cup and lid arrays.

Abstract: A thin film field effect transistor has an island of polysilicon on the surface of a substrate, preferably of an insulating material. A layer of silicon dioxide is on the surface of the substrate and surrounds the polysilicon island. The silicon dioxide layer is of substantially uniform thickness and contacts the edge of the polysilicon island. A gate insulator layer, preferably of silicon dioxide, of substantially uniform thickness is on the surface of the polysilicon island. A conductive gate, preferably of doped polysilicon, is on the gate insulator layer and extends across a portion of the polysilicon island. The portions of the polysilicon island at opposite sides of the gate are doped to form the source and drain of the transistor. The transistor is formed by applying a layer of polysilicon on the surface of a substrate and applying a mask over the portion of the polysilicon layer which is to form the island.

Abstract: A method for polishing the edges of a plurality of semiconductor wafers rotates a stack of wafers against a polish one or more pads such that both the wafer edges and the sides of the edges are polished to a mirror finish. The polish pad has a series of grooves through which the wafer edges are passed to polish the sides of the wafer edges, or two pads are used, one with grooves and one without grooves.

Abstract: A method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap.

Abstract: A multi-layered insulation film of non-doped CVD SiO.sub.2 (silicon dioxide) film and BPSG (boro-phospho-silicate glass) film is formed on a silicon substrate. Films have a contact hole exposing impurity diffused region formed in silicon substrate. A semiconductor layer is formed in the contact hole. An Al (aluminum) film is formed on the semiconductor layer. The semiconductor layer contacts the BPSG film so that the contact resistance between the semiconductor layer and the Al (aluminum) film can be reduced, and a variation of the contact resistance between respective semiconductor devices can also be reduced.