Abstract: A MIS transistor, has a semiconductor substrate of a first conduction type; a gate insulation film and a gate electrode which are selectively formed on the semiconductor substrate; an insulating film formed on the side surface of the gate electrode and on the semiconductor substrate; a first gate side wall layer provided on the upper surface and side surface of the insulating film and having a dielectric constant greater than that of the insulating film, the first gate side wall layer having a height smaller than that of the gate electrode; and a second gate side wall layer composed of an insulating film which covers the first gate side wall layer. This MIS transistor can be produced by a known LSI production technique employing self-alignment, without increasing the number of the steps of the process.

Abstract: An improved process for forming individual dies having faces that allow the dies to be assembled against other like dies to form one and/or two dimensional scanning arrays with minimal chipping and fracturing wherein the active side of a wafer is etched to form separation grooves with the wall of the grooves adjoining the die presenting a relatively wide surface to facilitate sawing, wide grooves are cut in the inactive side of the wafer opposite each separation grooves, and the wafer cut by sawing along the separation grooves, the saw being located so that the side of the saw blade facing the die is aligned with the midpoint of the wide wall so that on sawing the bottom half of the wall and the remainder of the grooves are obliterated leaving the top half of the wall to prevent cracking and chipping during sawing.

Abstract: A method of extracting an impurity profile from a diced semiconductor chip having cellular construction. The cells are arranged in a matrix the columns and rows of which have a defined column pitch a.sub.x and a defined row spacing a.sub.y. In accordance with the method, the diced chip is bevelled from its original surface to expose the cells. The two probes of a Spreading Resistance Profile (SRP) device are then placed in contact with the dopant regions of two cells in the same row of the matrix, the distance .DELTA.X between the probes being ma.sub.x, where m is an integer, and the total resistance R.sub.T between the probes is measured. The SRP device is then stepped through a plurality of rows in the matrix, contacting cells in the same two columns as in the case of the first measurement, thereby interactively generating a plurality of total resistance R.sub.T measurements. The total resistance R.sub.T measurements are then combined to obtain the doping profile of the dopant region.

Abstract: The inventive method is advantageously used in the manufacture of an article that comprises an opto-electronic device (e.g., LED or photodetector diode) that has a substantially planar radiation-emitting or receiving (first) surface region. The method comprises preliminarily positioning the end of a length of optical fiber relative to the first surface region, and causing radiation from a radiation source to be emitted from the fiber end so as to be incident substantially normally on the first surface region. A part of the radiation is reflected, collected by the fiber end, and transmitted to a power meter. The output of the power meter (or a quantity derived therefrom) is compared to a pre-determined measurement value and, if indicated by the comparison, the position of the fiber end is adjusted. A significant aspect of the invention is the existence of an easily measured relationship between the reflected power received by the power meter and the distance .DELTA.

Abstract: A method for connecting different conducting layers of a microelectronic device is disclosed.

Abstract: A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electrical and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield.

Abstract: This is a DMOS transistor and a method of forming a DMOS transistor structure. The method comprises: forming a polycrystalline silicon central gate region; forming a drain region in the substrate self-aligned to the central gate region; forming polycrystalline silicon gate sidewalls adjacent to the gate region; and forming a source region in the substrate self-aligned to the edges of the sidewalls. It can provide a channel region which is significantly longer (Ld) than it is in depth (essentially Lj) can be produced between the source region and the drain region, and thus the method provides an optimization of the transistor for lower on-resistance and thus a DMOS device having a MOS channel length longer than its parasitic JFET channel length. Preferably channel regions are formed which are 0.25-0.75 um in depth and the channel regions have an Ld of 1.0-2.5 um.

Abstract: A standard lead-frame has an aperture pierced to produce an opening sufficiently large to make room therein for the mounting of a semiconductor circuit chip. A heat sink for the semiconductor circuit chip is fastened into position in or just below the opening. The semiconductor circuit chip is then affixed directly to the heat sink. After wires have been bonded to connect contact areas of the chip to respective parts of the lead frame the unit is encapsulate such a fashion that a major surface of the heat sink protrudes from the encapsulation.

Abstract: A static random access memory device includes memory cells each having four MOS transistors and two load resistors which form a flip-flop circuit. The load resistor is formed by ion implantation of impurities in a predetermined region of an oxide film which is an extension of a gate insulating film of the MOS transistor. A power supply interconnection is connected to a surface of the load resistor. The word line and power supply interconnection are formed of a stacked structure having a polysilicon layer and a high melting metal silicide layer.

Abstract: Disclosed is a method for making self-aligned metal contacts on semiconductor devices, with a submicronic spacing between regions controlled by the contacts. On a semiconductor body supporting at least one raised pattern, a double layer of SiO.sub.2 and Si.sub.3 N.sub.4 is deposited by an isotropic method. A double ionic etching of Si.sub.3 N.sub.4 by SF.sub.6 and of SiO.sub.2 by CHF.sub.3 is done to insulate the sidewalls on the flanks of the pattern. A sub-etching by HF/NH.sub.4 F/H.sub.2 O creates a cap beneath each sidewall. The metal contacts, deposited by evaporation, are self-aligned and separated by a space "d" equal to the thickness of the insulating layers.

Abstract: A method and apparatus for deposition of an in-situ doped silicon film are disclosed. The deposition may be carried out in an LPCVD reactor, with the temperature of the chamber during deposition preferably closely above the decomposition temperature of silane gas. The preferred dopant source is tertiary butyl phosphine, since the deposition rate of in-situ doped silicon using this source is much greater than that using phosphine as the source, which allows low temperature deposition at reasonable rates. At a temperature of about 560.degree. Celsius, the phosphorous is better incorporated into the deposited film than in films deposited at higher temperatures, which allows the ratio of dopant gas to silane in the chamber to be lower; a low dopant ratio allows improved deposition thickness uniformity. The LPCVD reactor preferably has an injector tube therein which travels a distance within the reactor before its opening, through which the tertiary butyl phosphine passes.

Abstract: Silicon is used to create multi-chip carriers for integrated circuits. The process of fabricating the carriers uses standard integrated circuit fabrication equipment. Cavities are etched into a silicon wafer, metallization or polysilicon is deposited to electrically interconnect the cavities, and integrated circuit die are placed in the cavities. Traces connecting the integrated circuits are buried in channels formed in the silicon, which can be doped and biased to provide enhanced isolation between traces as well as control over the electrical characteristics of the traces. The traces can be formed in multiple layers of material placed on the wafer to provide additional communication capacity in the carriers.

Abstract: A low cost, lightweight, fast, dense and reliable extended integration semiconductor structure is provided by forming a thin film multilayer wiring decal on a support substrate and aligning and attaching one or more integrated chips to the decal. A support ring is attached to the decal surrounding the aligned and attached integrated substrate, and the support substrate is removed. Reach-through vias connect the decal wiring to the chips.

Abstract: It is desirable to implement complementary field effect transistors in group III/group V compound semiconductors, especially on InP substrates. Outstanding n-channel performance has been demonstrated in InGaAs channel devices on InP substrates. Preliminary experiments indicate that GaAsSb channel devices will result in optimal p-heterostructure FETs (HFETs). This disclosure teaches a technique to fabricate both n- and p-channel devices on the same substrate, allowing the demonstration of (C-HFET) technology. The HFET structure contains a channel region and the barrier region. The channel region consists of two distinctive parts: the p-channel and the n-channel areas. The p-channel area consists of GaAsSb, lattice matched to the InP substrate. In n-channel FETs, and ohmic contacts are formed by first doping the contact areas with Si by ion implantation, annealing the structure and then depositing and annealing the ohmic metal.

Abstract: Method for making an integrated guide/detector structure made of a semiconductive material.

Abstract: An improved process for formation of a capacitor in a trench formed in a semiconductor wafer is disclosed. The improved process comprises selectively implanting oxygen through the bottom surface of the trench into the region of the wafer adjacent the bottom surface of the trench and through the surfaces at the top corners of the trench into regions of the wafer adjacent such surfaces at the top corners of the trench using a plasma formed in a plasma-assisted etching apparatus while maintaining a high negative DC bias on the wafer being implanted. Subsequent growth of oxide on the surfaces of the trench will cause the implanted oxygen to form additional oxide in the implanted regions of the wafer adjacent the bottom surface of the trench and adjacent the surface at the top corners of the trench to compensate for the lower oxide growth rates in these areas.

Abstract: Photodetectors that produce detectivities close to the theoretical maximum detectivity include an electrically insulating substrate carrying a body of semiconductor material that includes a region of first conductivity type and a region of second conductivity type where the region of first conductivity type overlies and covers the junction with the region of second conductivity type and where the junction between the first and second regions separates minority carriers in the region of second conductivity type from majority carriers in the region of first conductivity type. These photodetectors produce high detectivities where radiation incident on the detectors has wavelengths in the range of about 1 to about 25 microns or more, particularly under low background conditions.

Abstract: A method is provided for manufacturing a semiconductor device at a face of a semiconductor layer having a first conductivity type. Over the semiconductor layer and insulating therefrom a gate conductive layer is formed, which has a predetermined pattern defining an opening. A well of a second conductivity type is then implanted into the face of the semiconductor layer by self-aligning to the sidewall of the gate conductive layer. A first surface region of the first conductivity type is formed within the well and self-aligned to the sidewall of the gate conductive layer. A sacrificial sidewall layer is formed in the opening which defines a second narrower opening, so that a subsurface region of the second conductivity type may be formed within the well self-aligned to the sacrificial sidewall layer. A second surface region of the second conductivity type is then formed substantially within the first surface region and self-aligned to the sacrificial sidewall layer.

Abstract: Large numbers of small sized, physically discrete, two-terminal non-linear devices, typically around 20 .mu.m across, are produced simultaneously, each exhibiting substantially identical physical and electrical properties by forming on the surface of a temporary support a multiple layer formation consisting of a series of thin film layers of selected materials and uniform thicknesses constituting a diode structure, for example a MIM type or p-n-p punch-through type structure; scribing the multiple layer formation in a regular pattern to define portions; and thereafter removing the support and separating the portions into physically discrete elements, each of which forms an individual non-linear device.

Abstract: A method of making a resin encapsulated pin grid array includes an IC chip mounted on a resin substrate having a plurality of contact pins on its lower surface and resin-encapsulated by injection molding. A metal heat radiating member is integrally formed on the upper surface of the encapsulating resin when the encapsulating resin is injection-molded.