Abstract: A thermal jet ink printing is provided with an improved printhead. The printhead is formed by monolithic integration of MOS logic elements and drivers onto the same silicon substrate containing the resistive elements using a more efficient manufacturing process. In a preferred embodiment, the logic switches, logic drivers and resistive elements are formed from a single layer of polysilicon with the resistive element formed on a thermally grown field oxide layer. The integrated circuit chips are formed by a MOS fabrication technology which uses fewer processing steps than used in existing chips, and the resulting chips are thermally stable and can be operated at higher logic voltages.

Abstract: A heterostructure diode is produced by a plasma CVD process. A defect caused on a silicon single crystal substrate by plasma deposition during formation of an amorphous semiconductor film leads to a problem of increase in the dark current due to the defect level. This defect is compensated for by active hydrogen contained in the amorphous semiconductor film so as to reduce the dark current. This can be effected by an annealing process conducted after formation of the heterojunction diode. The RF power is set low in the beginning period of formation of the semiconductor film. A radiation detecting apparatus is provided in which a plurality of the heterostructure diodes are integrated on a common substrate.

Abstract: A method of forming a contact hole in a semiconductor device while maintaining intended electrical isolation of electrical conductive material layers, even in the presence of mask misalignment/excessive etching which may occur during the fabrication process of the contact hole and the resulting device are disclosed. The method comprises the formation of an etch barrier layer to provide an isotropic etching barrier and an electrically insulating layer for the conductive material layers which are positioned proximate the contact hole. Thus, when the contact hole is formed by anisotropically etching to expose the surface of the diffusion region an electrical short cannot occur between conductive material layers proximate the contact hole and conductive material which is deposited into the contact hole.

Abstract: A process for forming the ridge structure of a self-aligned InP-system, double heterostructure (DH) laser, particularly useful for long wavelength devices as required for signal transmission systems includes a thin Si.sub.3 N.sub.4 layer (41) inserted between a photoresist mask (42) that defines the ridge structure, and a contact layer (35). Using a Si.sub.3 N.sub.4 layer (4) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si.sub.3 N.sub.4 layer (43) for device embedding, provides for the etch selectively required in the process step that is used to expose the contact layer to ohmic contact metallization deposition.

Abstract: A method and film/interconnect lead combination for attaching a plurality of sets of interconnect leads on a strip of film using an adhesive which loses bonding strength upon being exposed to energy such as heat or ultra violet light. The film holds the interconnect leads firmly in their proper position for bonding to an integrated circuit chip and to a leadframe or substrate such as a printed wiring board or a ceramic substrate for hybrid circuits. Either during or after bonding the interconnect leads to the leadframe or substrate, energy is applied to the adhesive holding the interconnect leads to the film and the film is detached from the interconnect leads in a manner which will not damage the leads due to the reduced adhesive strength. Thus, the leadframe package will not enclose the film.

Abstract: A complementary NPN and PNP contactless vertical transistor structure is formed by a process that includes the steps of providing: (1) a buried layer and P-- tub for NPN; (2) a channel stopper for NPN, and a buried layer for PNP; (3) isolation oxide for NPN and PNP; (4) a sink for NPN, and a ground for PNP; (5) a base for NPN, and a sink for PNP; (6) a base for PNP; (7) a N+ poly implant for NPN emitter and PNP extrinsic base; (8) a P+ poly implant for NPN extrinsic base and PNP emitter; (9) poly definition; (10) silicide exclusion for resistors and diodes; (11) contacts; (12) first metal; (13) vias; (14) second metal; and (15) scratch protection.

Abstract: A method of partially eliminating the field oxide bird's beak over a storage cell and slightly enlarging the storage cell active area without adding any process steps is described. A photomask is used during a buried contact etch to reduce the field oxide bird's beak both vertically and horizonally. The storage cell active area is further enlarged during a first polysilicon etch step without adding process steps. At that point, the wafer is completed by existing techniques.

Abstract: The invention provides a bipolar transistor structure on a buried oxide layer for use in an integrated circuit and a method for fabricating the same. The invention may be incorporated into a method for fabricating bipolar transistors in a BiCMOS structure. The bipolar transistor is constructed in two stacked epitaxial layers. The first epitaxial layer is used to form both the MOSFET and the buried collector of the bipolar transistor. The second epitaxial layer is grown as a blanket epitaxial layer. The intrinsic collector and the base of the bipolar transistor are formed in the second epitaxial layer. An oxide layer is formed over the base. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the second epitaxial layer.

Abstract: A process for the formation of a titanium nitride/cobalt silicide bilayer for use in semiconductor processing. Titanium and then cobalt are deposited on a silicon substrate by sputter deposition techniques. The substrate is then annealed. During this process the titanium first cleans the silicon surface of the substrate of any native oxide. During the anneal, the titanium diffuses upward and the cobalt diffuses downward. The cobalt forms a high quality epitaxial cobalt silicide layer on the silicon substrate. The titanium layer diffuses upward to the surface of the bilayer. The anneal is carried out in a nitrogen or ammonia ambient, so that a titaniun nitride layer is formed.

Abstract: A method of forming a transistor is disclosed. Conventional fabrication techniques direct an ion implantation beam toward a substrate upon which a gate has already been formed. If the gate stack is too low relative to the incident beam energy, the dopant species may channel thorugh the gate stack, adversely affecting transistor performance. The present invention prevents channeling through this gate by covering the gate with a protective layer before ion implantation.

Abstract: In a solid state image sensing device of p-conductivity type well, photo-electro converting region (1) are configurated to have larger area as depth increases, so that excessive electric charges generated in the p-conductivity type well are easily transferred from expanded peripheral parts (7) at the bottom (1b) to channel (3), without being undesirably transferred downward through thin p-conductivity type region 6 to substrate (4), and smear electric charges which has been generated in a thin p-conductivity type well under the photo-electro converting region in the conventional device is suppressed, to effectively decrease the smear phenomenon.

Abstract: Integrated circuits are formed by bonding two substrates together on a moat or recess. If the moat is exposed at a side wall, an optical fiber is inserted therein and communicates optically with a photoelectric device in the substrate by a slant side wall of the moat. If the moat is sealed by a cover layer resulting from removing all or most of the top substrate leaving the bonding layer as a cover, a pressure responsive device is formed on the cover layer directly or in the remaining top substrate over the sealed cavity.

Abstract: A method and apparatus for detecting a planar endpoint on a semiconductor wafer during chemical/mechanical planarization of the wafer. The planar endpoint is detected by sensing a change in friction between the wafer and a polishing surface. This change of friction may be produced when, for instance, an oxide coating of the wafer is removed and a harder material is contracted by the polishing surface. In a preferred form of the invention, the change in friction is detected by rotating the wafer and polishing surface with electric motors and measuring current changes on one or both of the motors. This current change can then be used to produce a signal to operate control means for adjusting or stopping the process.

Abstract: Disclosed is a process for producing a monolithic microwave integrated circuit device utilizing a body having a first thickness in the heat producing region and a second thickness in the region adjacent to the microstrip transmission lines.

Abstract: A semiconductor apparatus comprises a semiconductor body of one conductivity type; a first impurity region of an opposite conductivity type, which is formed in the surface area of the semiconductor body; impurity regions of the opposite conductivity type, formed in the surface area of the semiconductor body, at locations away from the first impruity region; second and third impurity regions of one conductivity type, which seve as source and drain regions, respectively, and are formed in the impurity regions of an opposite conductivity type, so as to sandwich a channel reigon; and a gate electrode formed on the channel region, through an insulative layer. In this semiconductor apparatus, the impurity regions of the opposite conductivity type include fourth and fifth impurity regions, formed in the channel region such that at least parts of the fourth and fifth impurity regions overlap.

Abstract: A polysilicon layer may need to have electrical characteristics which are relatively uniform from wafer to wafer. The use of polysilicon as a resistor is one such example. In order to obtain the requisite uniformity, the temperature of the wafers which are receiving the polysilicon must all be the same within a tight tolerance. The reaction takes place in a furnace which takes a long time to reach the requisite temperature tolerance. While the furnace is stabilizing the temperature, oxide, which is an insulator, is growing on the contact locations of the various substrates. To minimize the deleterious oxide formation, a thin layer of polysilicon is deposited at a time significantly prior to the time that the furnace stabilizes which ensures a good, low-resistance contact. The remainder of the polysilicon is then deposited on the thin layer of polysilicon after the temperature has stabilized to obtain the requisite wafer-to-wafer resistance uniformity.

Abstract: A method for forming a self-aligned horizontal transistor includes the step of first defining a narrow base contact on an isolated N-tank (10) to define a first reference edge (41). A layer of sidewall oxide (40) is then disposed on the vertical wall of the base contact (34) to define a second reference edge (42). An emitter well (44) and a collector well (46) are then defined on either side of the contact with the vertical wall of the emitter well (44) aligned with the reference edge (42). A dopant material is then disposed adjacent the reference edge (42) and the dopant diffused into the substrate from a lateral direction to form a P-type base region (58) with a graded impurity profile. N-doped regions (64) and (66) are then formed in the emitter and collector wells to form the emitter and collector of the transistor.

Abstract: The size of a fusible link (22C.sub.F) created from part of a metal layer (22) is controlled by an oxidation performed in a deposition chamber that is also used for depositing a dielectric layer (30) over the fuse structure. The metal layer serves as a diffusion barrier between semiconductor material (14 and 16) and another metal layer (24).

Abstract: Direct contact to shallow junctions in integrated circuits and interconnection between these contacts is achievable by utilizing a specific aluminum CVD process. In this process the aluminum is deposited utilizing a triisobutyl aluminum precursor onto a substrate having a nucleation layer, e.g. a titanium nitride layer. By appropriate choice of this nucleation layer to control the nucleation of the depositing aluminum, suitable contact is made while avoiding void defects present in the absence of such layer.

Abstract: Contacts to the gate electrode of a first field-effect transistor and the source/drain region of a second field-effect transistor are formed using a silicide as a local interconnect.