Abstract: Digital-signal-processing apparatus has a ringing-suppression-coefficient-generating device that generates a ringing suppression coefficient according to an amount of ringing occurred at an input signal, and a ringing suppression device that generates a ringing suppression signal based on high-frequency component of the input signal and the ringing suppression coefficient and suppresses the ringing by giving the ringing suppression signal to the input signal.

Abstract: A digital filter instruction and filter implementing the filter instruction are disclosed. The filter instruction synthesizes a digital filter and includes an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit. The filter instruction a concise instruction format to significantly decrease memory required, allow for instruction pipelining without branch penalty, and uses a circular buffer for the data so the data address pointer is only needed to be updated for the next input sample. The filter instruction may be used to implement FIR or IIR filters by using the options of pre-clear accumulator or pre/post storing accumulator results.

Abstract: Methods and systems for novel infinite impulse response filtering system to allow DC using a complex input signal having a real and imaginary part of the complex input signal yr and yi to produce a real part of a dispersion-compensated signal Xr. The system includes a first filtering circuit for filtering the real part of the input signal yr to produce a filtered real signal w1, a second filtering circuit for filtering and time reversing the imaginary part of an input signal yi to produce a filtered imaginary signal, and a first output summing device for summing the real and the imaginary filtered signal to produce the real part of a dispersion-compensated signal Xr. In an embodiment the filtering is accomplished with time reversing devices and real coefficient infinite impulse filters. In another embodiment, the filtering is accomplished with complex-coefficient infinite impulse filters.

Abstract: A multiple-word multiplication-accumulation circuit suitable for use with a single-port memory. The circuit is composed of a multiplication-accumulation (MAC) operator and surrounding registers. The MAC operator has multiplicand and multiplier input ports with different bit widths to calculate a sum of products of multiple-word data read out of a memory. The registers serve as buffer storage of multiple-word data to be supplied to individual input ports of the MAC operator. The amount of data supplied to the MAC operator in each clock cycle is adjusted such that total amount of data consumed and produced by the MAC operator in one clock cycle will be equal to or smaller than the maximum amount of data that the memory can transfer in one clock cycle. This feature enables the use of a bandwidth-limited single-port memory, without causing adverse effect on the efficiency of MAC operator usage.

Abstract: Low complexity (16 bit arithmetic) video compression has 8×8 block with transforms using 8×8 integer matrices and quantization with look up table scalar plus constant right shift for all quantization steps. Inverse quantization also a look up table scalar plus right shift dependent upon the quantization step and inverse transform using the 8×8 integer matrices.

Abstract: A programmable element for data processing comprises a crosspoint switch (318), a mathematical operation module (320), and a plurality of data hold modules (604,606). Each of the data hold modules (604,606) receives data from the crosspoint switch (318) and communicates the data to an input of the mathematical operation module (320) such that data arrives at the inputs of the mathematical operation module (320) substantially simultaneously. A first data hold module (604) communicates a first data valid signal to a second data hold module (606) upon receipt of first valid data, and the second data hold module communicates a second data valid signal to the first data hold module upon receipt of second valid data.

Abstract: Systems and methods compress and decompress 16 bit data. The 16 bit data may be signed or unsigned and represented in a fixed point or floating point format. A fixed block size of data is compressed into a fixed length format. Data compressed using a medium quality compression scheme may be efficiently decompressed in hardware. Data may be efficiently compressed and decompressed in hardware using a high quality compression scheme. The high quality compression scheme has a lower compression ratio compared with the medium quality compression scheme, but is near lossless in terms of quality.

Abstract: This invention relates to a short message format that captures useful information embedded in a data vector of sequence of symbols or numbers. The data vector may represent many different forms of information generated by various electronic and information systems. This short message format is particularly useful when bandwidth limited communication links are used to transmit a data set that can be represented as a set of data vectors that is true for essentially all types of data. Described herein is an algorithm formulated to be useful for data communication problems associated with bandwidth limited communication links.

Abstract: A method for generating an executable workflow code from an unstructured cyclic process model. The method comprises the following steps. First a continuation equation system is generated from the unstructured cyclic process model. Then, the executable workflow code is generated from the continuation equation system, wherein therefore, the continuation equation system is solved by means of transformation rules.

Abstract: A method and system to compensate for inaccuracy associated with processing values with finite precision includes a process for selecting a display value whereby an initial value is provided in a first numbering system. The initial value is then converted into an equivalent stored value in a second numbering system. Then a display value in the first numbering system is determined and selected such that the selected display value includes the least number of significant digits that convert from the first numbering system to the second numbering system exactly as the stored value. The selected display value in the first numbering system is then used for display and/or further processing when the stored value in the second numbering system is recalled.

Abstract: A data processing apparatus and method includes multiplier logic operable to multiply the first and second n-bit significands to produce a pair of 2n-bit vectors. Half adder logic is arranged to produce a plurality of carry and sum bits representing a corresponding plurality of most significant bits of the pair of 2n-bit vectors. The first adder logic then performs a first sum operation with a first rounded result and a second adder logic performs a second sum operation with a second rounded result. The required n-bit result is then derived from either the first rounded result or the second rounded result. The data processing apparatus takes advantage of a property of the half adder form to enable a rounding increment value to be injected prior to performance of the first and second sum operations without requiring full adders to be used to inject the rounding increment value.

Abstract: A system and method is provided for measuring lock usage in a non-intrusive manner. Measurements are performed only when a lock is contended. When a lock is requested and the lock is available (i.e., is not contended), the only data gathered is a counter that is incremented to keep track of the number of times the particular lock was requested. When a lock is contended, an operating system trace hook is requested. The trace hook records data such as the timestamp that the requester requested the lock, the request count, a stack traceback to identify the function corresponding to the requester, and the address of the lock that was requested. Post-operative processing analyzes the recorded trace hook data to identify contended locks and processes that may not be efficiently using locks.

Abstract: A system and method for providing self-installing software components for network service execution is presented. A basic communication framework is established with a service host system executing a network service software component to provide a network service. Availability of the network service software component is determined and prerequisites against a runtime environment are verified through the service host system. A code bundle providing the network service software component through the service host system logically grouped with installation instructions for the network service software component is executed.

Abstract: The present invention is an incremental umbrella sampling method to improve the performance of established sampling methods. It is sampling the state space by iteratively generating states xi,t and their weighting factors represented by Formula (a) by fitting the sampling distribution function ?j(x) of the next iteration to at least one weighted property of the already sampled states. This means that ?j(x) is fitted to the product represented by Formula (b), in which Formula (a) is the weighting factor and O(x,i) is a function respectively a property of the states xi,t. The number of states xi,t and the number of weighting factors (see Formula (a)) is incremented with each iteration. In order to have a consistent set of weighting factors (see Formula (a)), the weighting factors are recalculated in each iteration for all, respectively for a set of selected, states. By fitting ?j(x) in the state space it is possible to use all the information of Formula (a) and O(xi,t) for the states xi,t generated so far.

Abstract: Interpolators for quadratic approximation for sinusoids are described. A sample source providing first order derivatives of sub-sampled sets of phase factor samples is used. A differentiator is coupled to receive the first order derivatives and configured to provide second order derivatives of the first order derivatives. A first scaling device is coupled to receive each of the first order derivatives. A second differentiator is coupled to receive each of the first order derivatives and configured to respectively provide second order derivatives of the first order derivatives. A second scaling device is coupled to receive the second order derivatives. A first integrator is coupled to receive output from the first scaling device for preloading, and to receive output from the second scaling device for integration. A third scaling device is coupled to receive output from the first integrator. A second integrator is coupled to receive output from the third scaling device.

Abstract: A system consistent with this invention evaluates the performance of a module via a network. Such a system comprises an evaluation module, an evaluation module computer running an end user interface for interfacing with the evaluation module computer, wherein the evaluation module computer evaluates the performance of the module, a terminal linked to the evaluation module computer through a network, wherein the terminal displays the end user interface, and a shadow terminal linked to the evaluation module computer through a network, wherein the shadow terminal displays the end user interface.

Abstract: A operator is located between two converters that convert data between floating-point format and a predetermined format. The operator operates on predetermined format data, which consists of the same sign bit, the same exponent, and the two's complement of the mantissa of the corresponding floating-point data. When the operator is an arithmetic logic unit (ALU), the number of operations for a given calculation can be reduced.

Abstract: A method includes running a debugging tool in regard to a program which is undergoing debugging. The program may support multi-threaded operation. The method further includes presenting an option to a user via the debugging tool with respect to a program instruction in a first thread of the program. The program instruction may be for putting an item of data into a queue. The method also includes, if the user exercises the option, identifying a program instruction in a second thread of the program. The second thread is different from the first thread. The identified program instruction in the second thread may be for getting the item of data from the queue. The method further includes stopping execution of the program at the identified program instruction in the second thread.

Abstract: A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

Abstract: A system and method installs a computer program, as well as the environment in which the computer program operates, if such environment is not already installed. The program as well as its environment are obtained via one or more servers and a computer network.