Abstract: Systems and methods for converting a data stream from a first sample rate to a second sample rate using a sample rate converter that employs selectable filters. In one embodiment, the filters are implemented by providing multiple sets of filter coefficients in a memory, selecting one of the sets of filter coefficients and performing coefficient interpolation to produce filter coefficients that are convolved with the input data stream to produce a re-sampled output data stream. The input signal can be an audio signal that is convolved with interpolated polyphase filter coefficients in the sample rate converter of a digital PWM audio amplifier. The set of filter coefficients can be selected by a value stored in a filter selection register that is modifiable by a DSP or by user input. The sets of filter coefficients can be stored in a single memory and interpolated according to a cubic spline interpolation algorithm.

Abstract: The disclosure describes a method for performing a fixed point calculation of a floating point operation (A // B) in a coding device, wherein A // B represents integer division of A divided by B rounded to a nearest integer. The method may comprise selecting an entry from a lookup table (LUT) having entries generated as an inverse function of an index B, wherein B defines a range of values that includes every DC scalar value and every quantization parameter associated with a coding standard, and calculating A // B for coding according to the coding standard based on values A, B1 and B2, wherein B1 and B2 comprise high and low portions of the selected entry of the LUT. The techniques may simplify digital signal processor (DSP) implementations of video coders, and are specifically useful for MPEG-4 coders and possibly others.

Abstract: A method includes personalizing a software installation file. The personalizing includes providing the file with a unique identifier included as part of a file name associated with the file. Another method includes installing a software application from the personalized installation file, extracting the indication from the file name and using the indication to personalize the software application.

Abstract: A method, information processing system, and computer readable medium for annotating graphs to allow for subsequent quick loading and analysis of very large graphs is described. The present invention encompasses a way to order and annotate nodes of a graph into a data stream that allows for optimization of subsequent processing of nodes in later analysis. For example, a very large reference graph representing heap snapshots may be annotated to facilitate post-processing and visualization of the heap for memory leak analysis. In such an example, the present invention reduces the number of objects and references to be modeled in memory, while still capturing the essence of the non-modeled portions. In this example, the present invention may process reference graphs on the scale of one hundred million live objects per snapshot using a computer with one gigabyte of memory.

Abstract: The present invention discloses a fast Fourier transform (FFT) processor based on multiple-path delay commutator architecture. A pipelined architecture is used and is divided into 4 stages with 8 parallel data path. Yet, only three physical computation stages are implemented. The process or uses the block floating point method to maintain the signal-to-noise ratio. Internal storage elements are required in the method to hold and switch intermediate data. With good circuit partition, the storage elements can adjust their capacity for different modes, from 16-point to 4096-point FFTs, by turning on or turning off the storage elements.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention provide an improved technique for analyzing statements that use pointer or array syntax to access dynamically-allocated arrays to determine whether the statement generates a reference that is outside the bounds of the array's allocated memory. Statements that use pointer or array syntax to access dynamically-allocated arrays can be either statically (at compile-time) or dynamically bounds (at run-time) checked. Methods and systems in accordance with the present invention determine at compile-time if an array reference can be determined to always be in bounds or definitely out of bounds at least once, and if not, insert code into the program to check the array bounds dynamically at run-time before the access of the array reference.

Abstract: In one embodiment, a system for customizing executable software code is provided. The system can include a scan logic configured to scan the executable software code to determine an execution trigger point in the executable software code. A packager logic can be configured to alter the execution trigger point by embedding, into the executable software code, alternative code configured to cause a customized logic to execute at the execution trigger point.

Abstract: In a method for the optimisation of compiler-generated program code, the compiler-generated program code is searched for program code fragments which correspond, at least in their effect, to respectively one library code fragment contained in a predefined library. The program code fragments found thereby are replaced by respectively one call of the corresponding library code fragment. A computer program product comprises program instructions for the execution of this method. A portable data carrier contains both the program code optimised according to this method and the library.

Abstract: A collaborative development environment includes an integrated development environment and a collaboration client integrated into the environment. There also is a Help menu of a software application which includes sections to provide information about the software application and a peer support section to provide access to a collaboration server.

Abstract: The invention relates to a system and a method for tracing and evaluating the communication of software applications, especially MES applications in an entire system. The tracing and evaluation can be carried out progressively or step-by-step on a project level, an adapter level and a port level, i.e. individual communication connections and individual applications, but the entire project is also traced by (even heterogeneous) application environments. The tracing and evaluation mechanisms enable higher-level services to access online the archived trace and error data at all times. An example of one such service is the generation of a report in the pharmaceutical field, indicating the materials used and sent in production orders.

Abstract: A computer system is configured to create a product matrix of data from two matrices of data through the use of a representation in a group algebra. The matrices are represented in a group algebra based on a mathematical group adhering to certain criteria. Then the representations are mapped to vectors in a multidimensional vector space where their product can be obtained by reduction into a block-diagonal matrix multiplication which can be recursively computed by the same process. Multiple matrix multiplications can also be performed simultaneously though selection of a group which satisfies certain properties. Through this process, computational time improvements are obtained.

Abstract: A method and circuit for fast flag generation. The circuit is coupled to receive data to be shifted, the data including a first plurality of bits. A shift count value (including a second plurality of bits) is also received by the circuit, as well as an indication of a direction the data is to be shifted. Based on the shift count value and the indication of direction, the position of a bit within the data is determined. The bit is then output as a flag bit.

Abstract: Methods and apparatuses for automatic system setup. At least one embodiment of the present invention stores the setup configuration information (e.g., in files and/or in directory servers). The setup configuration information is stored (e.g., using a configuration file naming scheme) so that the configuration information for a particular machine can be found. A setup daemon on the machine searches for suitable configuration information in a number of places, such as: in a location in a local file system, in locations in mounted file volumes, and directory servers. The configuration information may be encrypted, and the setup daemon searches for the decryption key in a similar fashion.

Abstract: An apparatus and method for integer to floating-point format conversion. A processor may include an adder configured to perform addition of respective mantissas of two floating-point operands to produce a sum, where a smaller-exponent one of the floating-point operands has a respective exponent less than or equal to a respective exponent of a larger-exponent one of the floating-point operands. The processor may further include an alignment shifter coupled to the adder and configured, in a first mode of operation, to align the floating-point operands prior to the addition by shifting the respective mantissa of the smaller-exponent operand towards a least-significant bit position. The alignment shifter may be further configured, in a second mode of operation, to normalize an integer operand by shifting the integer operand towards a most-significant bit position. The second mode of operation may be active during execution of an instruction to convert the integer operand to floating-point format.

Abstract: Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. Soft information is passed among variable nodes and parity-check nodes. A low-voltage high-swing Max WTA circuit is also provided. The circuit can be implemented by short channel MOSFET transistors and yet provide a reasonably high degree of accuracy. Applications include soft computing, and analog signal processing, in general. A Min WTA circuit can also be built based on this circuit by subtracting the input currents from a large reference current.

Abstract: Aspects provide discrete-time analog, digitally programmable filtering. A filter includes a plurality of transistors coupled as a current mode circuit. Further included is a switch for use in switching the plurality of transistors in and out to tune the current mode circuit, wherein adjustable low bandwidth filtering using small silicon area without passive components is achieved.

Abstract: A look-up table which is required during looking up table for data transferring and a method for looking up table are provided. The method reduces the size of the look-up table used in the method for looking up table by simplifying the calculations. A reasonable error range is obtained for the required look-up table by adjusting appropriate modifiers. The method can be applied in the method for looking up table similar to the Q ? ( x ) = x B A calculation in the digital signal coder/decoder (CODEC), where both A and B are integers, and the calculation is more efficient if B/A is close to 1 or smaller than 1.

Abstract: A multi-operand decimal adder is described that performs addition on multiple binary coded decimal (BCD) operands. The multi-operand decimal adder uses binary carry-save adders to produce intermediate sums and carries, and outputs a decimal result based on the intermediate sums and carries. In various configurations, the multi-operand decimal adder may perform speculative or non-speculative binary carry-save addition. The multioperand decimal adders achieve a reasonable critical path. As a result, the decimal adders and the techniques described herein may be especially suited for numerically intensive commercial applications, such as spreadsheet or financial applications where large amounts of decimal data typically need to be processed quickly.

Abstract: A method and system for evaluating software includes generating a test deck (310), where the test deck is formulated to test the software for compliance with delivery system operation procedures (315), processing the test deck with the software, and grading the performance of the software for compliance with delivery system operation procedures (320).

Abstract: The state transition of a linear feedback shift register (LFSR) controlled by a clock (310) with length N and step size W, W being at least two, is accomplished via a next-state function (320). The next-state function deploys a state transition matrix (350). The state vector (330), which represents the contents of the LFSR, is either multiplied sequentially by the state transition matrix or multiplied by the state transition matrix to the power of W (multiple state transition matrix). The method and the LFSR according to the invention are characterized in that the multiple state transition matrix is decomposed in a first matrix (360) and a second matrix (370), the first matrix comprising at most N+W+1 different expressions and the second matrix comprising at most N+W+1 different expressions. The LFSR further comprises means to multiply the state vector by the second matrix and the first matrix, and means for computing the first matrix.