Abstract: An apparatus for scaling numbers comprises register means for storing an operand to be scaled, bit shifting means for performing a right shift operation on the operand, rounding means, and decision means to test for the existence of at least one of an overflow and an underflow condition.

Abstract: An apparatus comprising an address generation circuit, a lookup table, a multiplexer and an output circuit. The address generation circuit may be configured to generate a series of addresses. The lookup table may be configured to generate one or more coefficients in response to the addresses. The multiplexer circuit may be configured to generate one or more shifted values in response to (i) the coefficients and (ii) the one or more operands. The output circuit may be configured to generate an output signal by combining one or more component values in response to said shifted values. The coefficients are grouped as one over power of 2 components into mutually exclusive groups.

Abstract: The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register.

Abstract: Dynamic binary translators enable binaries of a source platform to execute on a target platform without recompilation. This is achieved by runtime (on-the-fly) translation of source machine instructions into equivalent target machine instructions. Typically dynamic binary translators are used for migrating from an older platform to a newer one, implementing complex instruction set architectures, speeding up simulators and in profiling tools. In all these applications, the speed of translation is critical to ensure that the overheads incurred by the translator do not outweigh the advantages of dynamic translation. One such overhead is created by the analysis required when code is translated for execution in a parallel processing environment.

Abstract: The first and second n-bit significands are multiplied producing a pair of 2n-bit vectors, and half adder logic produces a corresponding plurality of carry and sum bits. A product exponent is checked for correspondence with a predetermined exponent value. A sum operation generates a first result equivalent to the addition of the pair of 2n-bit vectors. First adder logic uses corresponding m carry and sum bits, the least significant of them carry bits being replaced with the increment value prior to the first adder logic performing the first sum operation. Second adder logic performs a second sum operation and uses the corresponding m?1 carry and sum bits replacing the least significant m?1 carry bits with the rounding increment value prior to the second adder logic second sum operation. The n-bit result is derived from either the first rounded result, the second rounded result or a predetermined result value.

Abstract: A data processing apparatus and method are provided for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result. The data processing apparatus comprises multiplier logic for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors, and sum logic operable to perform a sum operation to add a first set of bits of each of the pair of 2n-bits vectors. Sticky determination logic is also provided for determining from a second set of bits of each of the pair of 2n-bit vectors a sticky value, and selector logic is then used to derive the n-bit result from the output of the sum logic with reference to the sticky value.

Abstract: A signal is filtered by multiplying its Fourier transform by the Fourier transform of a reference sequence to which the filtering is to be matched. The reference sequence (e.g. a Golay sequence pair) is defined as an iterative combination of shorter sequences and its Fourier transform is generated by an iterative process of combining the Fourier transforms of a shorter starting sequence.

Abstract: A cyclic equation setting unit transforms and sets a Taylor series equation for calculating a sine function into a single cyclic equation common to terms of the Taylor series equation, the single cyclic equation having a new known number Q that is defined by multiplying a known number Q and the square of a variable X, shifting the result by a shift number S and then adding a constant K thereto. An adjustment unit adjusts and prepares the shift number S such that within a variation range of the variable X the variable X has a maximum value 1 with the constant K being not greater than 1. A cyclic equation executing unit inputs and converts angle information i to the variable X, and executing the cyclic equation in sequence from higher order term to lower order term for the number of terms of the Taylor series equation to derive a sine function of the angle information i.

Abstract: Methods, devices, and systems provide random number generation. Electrical characteristics of a processing device are sampled for statistically random values. The values are combined to produce random numbers. The random numbers are vended from the processing device for subsequent consumption by applications executing on or interfaced to the processing device.

Abstract: A sine wave multiplication circuit multiplies an analog input signal by n (n is an integer equal to or greater than 2) weighting coefficients each having a unique value. The polarity of the analog input signal multiplied by one of the n weighting coefficients is changed over. Further, changeover among the n weighting coefficients and of the polarity is performed after every sampling period equal to ½k (k is an integer, and 2k is equal to or greater than 6 but equal to or smaller than 4n) of one period of the sine wave signal by which the analog input signal is multiplied. As a result, a staircase waveform having 2n positive and negative stairs is generated while unnecessary harmonic wave components in the proximity of the sine wave signal by which the analog input signal is multiplied can be reduced.

Abstract: A method and apparatus are provided for automatically integrating software components for use in a COM compliant application from functions developed outside of the COM compliant application environment. The method and apparatus provide a user interface and a build tool that allows the user to select desired functions and select desired locations in the COM compliant application and map those locations to inputs and outputs of the function and create the component automatically from the user's selections. The method and apparatus provide a graphical user interface for the user to direct a build tool to generate the desired component and integrate that component with the COM compliant application.

Abstract: Provided are a simplified 4:2 carry save adder (CSA) cell and a 4:2 carry save adding method. The 4:2 CSA cell is formed of an odd detector and first through sixth switches through logic optimization. The odd detector generates an XOR of the first through fourth input signals, outputs the XOR as an odd signal, generates an XOR of the first and second input signals, and outputs the XOR as a first XOR signal. The first switch outputs the third input signal as a carry output signal in response to the first XOR signal. The second switch outputs the first input signal as the carry output signal in response to an inverted first XOR signal. The third switch outputs the carry input signal as a carry signal in response to the odd signal. The fourth switch outputs the fourth input signal as the carry signal in response to an inverted odd signal. The fifth switch outputs an inverted carry input signal as a sum signal in response to the odd signal.

Abstract: Methods and systems of detecting vulnerabilities in source code using inter-procedural analysis of source code. Vulnerabilities in a pre-existing source code listing are detected. The variables in the source code listing are modeled in the context of at least one of the inherent control flow and inherent data flow. The variable models are used to create models of arguments to routine calls in the source code listing. The source code listing is modeled with a call graph to represent routine call interactions expressed in the source code listing. The arguments to routine calls are modeled to account for inter-procedural effects and dependencies on the arguments as expressed in the source code listing.

Abstract: Efficiently implemented multi-channel integrators and multi-channel differentiators utilize a delay section in a single integrator or differentiator in lieu of parallel integrator or differentiator lines to handle multi-channel data flow and processing. The delay section functions like a shift register, greatly reducing the space and/or resources required for implementing the integrator or differentiator. Such integrators and differentiators can be used in multi-channel decimators, interpolators and numerically controlled oscillators in place of multiple instances of single channel integrators that have had to be used in earlier systems. These structures and devices can be implemented in programmable devices such as PLDs and similar devices, in which the delay section can be implemented in embedded memory in the device. Multi-stage decimators and interpolators can use multiple instances of an integrator and/or differentiator in series.

Abstract: An apparatus generates a debugger script to output first data corresponding to a symbol name for a breakpoint in a software program compiled as optimized code. A debugger script to output second data corresponding to the symbol name for the breakpoint in the software program compiled as unoptimized code is also generated. The apparatus further compares the first data to the second data, and indicates whether there is a difference between the first data and the second data.

Abstract: A method for debugging a process in a workflow engine, wherein the process includes a plurality of activity points, includes steps of: attaching to a running business process being controlled by the workflow engine; initiating a debugging session; receiving a set of breakpoints to be inserted into designated points in the process; stopping the running of the process at one or more of the breakpoints; and presenting a user with information relating to where the process has stopped and the status of the process flow.

Abstract: The present invention relates to an information apparatus and method suitable for use in upgrading control programs readily by a user. In step S501, a storage area to store an upgraded firmware is determined. In step S502, the upgraded firmware is provided. In step 503, the provided firmware is decrypted and re-encrypted. In step S504, re-encrypted firmware is written into the storage area determined in step S501. In step S505, a maximum marker is detected. In step S506, a value obtained by adding 1 to the maximum marker provides the marker corresponding to the storage area in which the firmware was stored in step S504. The present invention is applicable to, for example, an audio data server.

Abstract: A digital signal, x(n) (where n is an integer), is decimated by determining a signal vector, y(k), of size M by partitioning samples of the digital signal, x(n) according to sampling phases of the samples. The signal vector, y(k), is projected onto an N-dimensional sub-space, wherein N is an integer and N<M. Where the digital signal is generated by means of oversampling, it is possible to perform decimation in a way that optimizes the signal-to-noise ratio (SNR) of the decimated signal by suitably determining the sub-space onto which the signal vector will be projected.

Abstract: A method and a circuit for normalizing an initial bit flow, provided by a noise source, comprising dividing the bit flow into words of identical lengths, and assigning to each bit word of the initial flow an output state, the occurrence of a word, all the bits of which have identical states, alternately resulting in the assignment of a first state or of a second one.

Abstract: The derivative of a noise-containing input signal is determined by using an aliased derivative to periodically reset a filtered version of a normally determined derivative. The aliased derivative is calculated using a slower update or sampling rate than the normally determined derivative, and the filtered version of the normally determined derivative is reset to a reset value at each update of the aliased derivative. The reset value is based on a weighted sum of the aliased derivative and the filter output. The periodically reset filter output closely follows an idealized derivative of the input signal, substantially eliminating the phase delay introduced by conventional filtering.