Abstract: A system and method, useful in tracing program execution, for serializing data, such as an object data, into consistent, structured (e.g., XML) output. A serializer processes an object's data, and for each set of data, records the object's data in a structured (e.g., XML) format that reflects the object's current state. Nodes corresponding to fields and properties of the object are nested in the structure. Simple types define nodes with the current data value associated with the tag. More complex types including arrays, collections, dictionaries and exceptions are stored as individual members of a type, with any complex members further broken down into sub-nodes. Object data including custom collections, dictionaries, non-public fields and properties and properties with only get-accessor are serialized. The resulting output, such as in an XML formatted structure, is easy to read by humans, and is easily processed, such as for automated analysis purposes.

Abstract: Disclosed herein is a system for optimizing distribution of information employing a universal dictionary. Optimization may include reducing data communicated between a sender and a receiver when both employ the same (or similar) universal dictionary. The universal dictionary may be a reference frame available to the sender as well as the receiver, deviation from which constitutes data that may be communicated to the other party (sender or receiver). Use of the reference image by a flash manager in an electronic device to create a new flash image may reduce the size of any update package to be transferred to an electronic device from a flash image server and may also reduce time to transfer the update package and time taken to update FLASH memory in the electronic device. The reference image in the electronic device may also contain significant portions of the binary image.

Abstract: A data processing apparatus having data cache performs an N-point radix-R Fast Fourier Transform. If the data set is smaller than the data cache, the data processing apparatus performs the Fast Fourier Transform in logRN stages on all the data set in one pass. If the data set is larger than the data cache but smaller than R times the data cache, the data processing apparatus performs a first stage radix-R butterfly computation on all the input data producing R independent intermediate data sets. The data processing apparatus then successively performs second and all subsequent stage butterfly computations on each independent intermediate data set in turn producing corresponding output data. During the first stage radix-R butterfly computations, each of R continuous sets are separated in memory by memory locations equal to the size of a cache line.

Abstract: A method for applying a computation utilizing a processor (112) capable of accessing an on-chip memory (114) and data from an off-chip source (116), the method comprising the iterative steps of retrieving at the on-chip memory (114) successive frames of input data from the off-chip source (116); computing from a current input frame of data (30) available in the on-chip memory current result elements for completing a current output frame of results (33, 34, 35), and pre-computing from the current frame of input data future result elements for contributing to at least one future output frame of results.

Abstract: Disclosed herein is an update package generator which may employ a bank order determination module to determine an optimum bank order of memory banks of a binary image of at least one of firmware and software. The bank order may subsequently be employed in generation of an update package, wherein the size of the update package generated by the generator may be minimized. A bank order determination unit may selectively employ one of genetic algorithms and differential evolution techniques to determine an optimum bank order. Other parameters may also be employed in the generator. The generator may also be selectively optimized to employ at least one genetic evolution technique.

Abstract: An exemplary media implementation precipitates a device to perform actions including: determining if an instruction of a line of common intermediate language (CIL) code meets a predetermined exception-related criterion; and if so, injecting a decision point in association with the instruction of the line of CIL code, the decision point enabling a decision as to whether an exception is to be thrown with respect to the instruction. An exemplary device implementation includes: instrumented CIL code that includes a test couplet corresponding to a decision point and an associated instruction, the associated instruction capable of causing a fault; a decision runtime library that is adapted to evaluate the test couplet to selectively decide whether to throw an exception with respect to the associated instruction; and a common language runtime component that interprets the decision point so as to call the decision runtime library prior to executing the associated instruction.

Abstract: A Montgomery modular multiplier receiving a multiplicand (A), a modulus (M), and a multiplier (B), using a t-s compressor, where t>3 and s>1, and a multiplication method performed in the same. In response to a carry propagation adder signal, the t-s compressor performs additions on the carry C and the sum S and obtains the final results in a carry propagation adder structure.

Abstract: Method and apparatus for true random number generation is described. One aspect of the invention relates to a digital logic circuit that includes N logic gates, where N is an integer greater than two. For each logic gate in the N logic gates: a first input terminal thereof is coupled to an output terminal thereof; a second input terminal thereof is coupled to an output terminal of a left neighbor thereof; and a third input terminal thereof is coupled to an output terminal of a right neighbor thereof. A sampling logic circuit may be provided to sample the output of the N logic gates to produce N-bit binary numbers. The N-bit binary numbers are true random numbers produced using pure digital logic without using an external source of randomness. A linear hybrid cellular automaton (LHCA) may be provided for scrambling output data of the sampling circuit.

Abstract: A device for and method of generating an uncorrelated pseudo-random bit sequence by first selecting a user-definable value K. Next, factoring K+1 into m prime factors q1, q2, . . . , qm, where q1, q2, . . . , qm are ordered from smallest value q1 to largest value qm. Next, generating m pseudo-random sequences r1, r2, . . . , rm, where each pseudo-random bit sequence ri is uniformly distributed over a range (0, . . . , qi?1), and where i=1, 2, . . . , m. Finally, generating the uncorrelated pseudo-random sequence as R=r1+q1r2+q1q2r3+ . . . +q1q2 . . . qm?1rm.

Abstract: An apparatus and method for computing a SHA-1 hash function value are provided. The apparatus includes a first register unit including a plurality of registers that store a first bit string of predetermined lengths for generation of a hash function value; a second register unit storing input data in units of second bit strings with predetermined lengths, and sequentially outputting the second bit strings; a third register unit performing an operation on the first bit string of the plurality of registers and the second bit strings output from the second register unit so as to generate and store a third bit string, and updating first-bit string of the plurality of registers based on the third bit string; and an adding unit combining the first bit string stored in the first register unit, the first bit string of the third bit string stored in the third register unit, and the original initial values stored in the first register unit so as to obtain a hash function value.

Abstract: A method and apparatus for designing low-order linear-phase IIR filters is disclosed. Given an FIR filter, the method utilizes a new Krylov subspace projection method, called the rational Arnoldi method with adaptive orders, to synthesize an approximated IIR filter with small orders. The method is efficient in terms of computational complexity. The synthesized IIR filter can truly reflect essential dynamical features of the original FIR filter and indeed satisfies the design specifications. In particular, the linear-phase property is stilled remained in the passband.

Abstract: An apparatus, system and method for retaining the maximum speed of flip-flop metastability based random number generators includes a fixed delay unit having an input for receiving a common signal from a digital signal generator, and a variable delay unit having an input also for receiving the common signal from the digital signal generator. Each of the delay units is attached to the input of a respective logic gate. A frequency measurement of the occurrences of metastability, which is the speed of the random bit generation and delay tuning module 312 receives an output of one of the first NAND gates, checks the frequency of random number bit generation and updates the variable delay unit to according to predetermined criteria to tune the delay so as to maximize the speed of the random bit generation. An algorithm is used to determine whether the optimum delay is equal to, smaller or larger than the delay used to achieve the measured frequency.

Abstract: A random number generator includes a plurality of groups of independent flip flops, each of the groups having different configurations. Each of the outputs of the plurality of groups of flip flops being connected in an exclusive-or (XOR) arrangement, with a latch connected to the output of the DXOR. A metastable output of at least one of the flip flops causes a random signal to be output by the XOR for random number generation. The groups of flip flops can be divided into equally-sized groups, or unequally-sized groups with different configurations, such as the cross-connecting of NAND gates with or without buffers inserted between the data and clock signals, or inserting buffers between a data line of at least one NAND gate of each of the pairs of NAND gates being connected, or inserting a buffer between clock input of at least one NAND gate of each of the pairs of NAND gates being connected via a buffer. Capacitive loading and cross-connected buffers may also be used to induce varying delays.

Abstract: The invention relates to a method for replacing old software (10) that is in use with new software (12), which permits the maximum availability of the software. Said method is subdivided into a preparation phase (V) and an active phase (A). The preparation phase (V) take place during the operation of the old software (10). The active phase (A) is merely characterized by the execution of a MOVE command.

Abstract: A method for formatting an object file including generating a trace object code from trace source code, and processing component information of the trace object code to generate the object file, wherein the object file comprises a linear sequence of bytes comprising a file header, a plurality of section headers, and a plurality of section data entries.

Abstract: The circuit of this invention performs clock division with dynamic divide-by value change capability. This circuit provides low area and low latency. The clock divider is conventional except for the logic that handles the dynamic divide-by value change. When the divide-by value is changed by the user, such as through software, the changed value is recorded in a register but does not affect the divider immediately. Once the changed divide-by value is recorded, the divider clock output is allowed to continue till it reaches ‘low’ and is shut off. Then the recorded value is sent to the divider. The divider then generates a clock signal corresponding to the new divide-by value. The clock gating is then disabled and the clock propagates. This implements glitch free clock switching. This implementation of clock selection or switching provides low area and low latency for switching.

Abstract: During debug operations in one embodiment of a trusted subsystem, passwords may be used to enable and disable access to selected areas, and to make access by different entities mutually exclusive. In another embodiment, programmable units may be used to define what the selected areas of access are for debug operations.

Abstract: A system and method is provided for measuring lock usage in a non-intrusive manner. Measurements are performed only when a lock is contended. When a lock is requested and the lock is available (i.e., is not contended), the only data gathered is a counter that is incremented to keep track of the number of times the particular lock was requested. When a lock is contended, an operating system trace hook is requested. The trace hook records data such as the timestamp that the requestor requested the lock, the request count, a stack traceback to identify the function corresponding to the requestor, and the address of the lock that was requested. Post-operative processing analyzes the recorded trace hook data to identify contended locks and processes that may not be efficiently using locks.

Abstract: In preparing inlined program code for compiling, a synchronization depth is recorded in a table for ranges of program counter addresses. Furthermore, a stack frame is dedicated for the recordation of references to objects locked during the execution of the code. Such references are recorded in the stack frame at a location based on synchronization depth. When an exception occurs, the synchronization depth may be determined from the table and used to obtain, from the stack frame, a reference to an object from which a lock should be removed.

Abstract: This invention is about engineering approach to development of transactional workflow applications and about ability of this way produced applications to concurrently process large number of workflow requests of identical type with high speed. It provides methods and articles of manufacture: for graphical development of fully executable workflow application; for producing configuration of class objects and threads with capacity for concurrent processing of multitude of requests of identical type for transactional workflow and for concurrent execution and synchronization of parallel workflow-activity sequences within processing of a workflow request; for application self-scaling up and self-scaling down of its processing capacity; and for real-time visualization of application's thread structures, thread quantity, thread usage, and scaling-enacted changes in threads structure and quantity.