Patents Examined by Michele Fan
  • Patent number: 11189550
    Abstract: A low-cost semiconductor package using a conductive metal structure includes a lead frame including a pad and a lead, a semiconductor chip attached onto the pad of the lead frame, an Aluminum (Al) pad formed on the semiconductor chip, a clip structure having one side adhered to the Al pad and the other side adhered to the lead of the lead frame, and a sealing member formed to surround the semiconductor chip and the clip structure via molding, wherein the semiconductor chip is adhered directly to a junction of the lead frame through a first adhesive layer formed of a solder or epoxy resin-based material and is adhered directly to a junction of the Al pad and the clip structure through a second adhesive layer formed of a solder-based material.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 30, 2021
    Assignee: JMJ Korea Co., Ltd.
    Inventors: Yun Hwa Choi, In Suk Choi
  • Patent number: 11177200
    Abstract: A package includes a corner, a device die having a front side and a backside, and a molding material molding the device die therein. A plurality of redistribution lines is on the backside of the device die. The plurality of redistribution lines includes a plurality of metal pads. A polymer layer contacts the plurality of metal pads. A plurality of openings is formed in the polymer layer, with the plurality of metal pads aligned to and exposed to the plurality of openings. The plurality of openings includes a corner opening that is elongated and an additional opening farther away from the corner than the corner opening. The additional opening is non-elongated.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11177285
    Abstract: A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 16, 2021
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kangguo Cheng, Rama Divakaruni
  • Patent number: 11177390
    Abstract: An electronic device can include a panel; a driver circuit configured to drive the panel; and a transistor disposed in the panel, the transistor including a first electrode disposed on a substrate, an insulation pattern disposed on the substrate, the insulation pattern overlapping with an edge of the first electrode, a second electrode disposed on an upper surface of the insulation pattern, an active layer disposed on the first electrode, the insulation pattern and the second electrode, a gate insulating film disposed on the active layer, and a gate electrode disposed on the gate insulating film, in which a first portion of the active layer overlaps with the first electrode, a second portion of the active layer overlaps with the second electrode, and a channel area of the active layer is between the first portion of the active layer and the second portion of the active layer, and the channel area includes a first channel portion disposed along a side surface of the insulation pattern, and a second channel por
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: November 16, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: InTak Cho, JungSeok Seo, SeHee Park, Jaeyoon Park, SangYun Sung
  • Patent number: 11177448
    Abstract: The present disclosure provides a flexible display device and a manufacturing method. The manufacturing method includes: forming a layer of flexible display devices on a support plate; etching the layer of flexible display devices on the support plate to expose a portion of the support plate at a cutting region, the cutting region being a predetermined region between two adjacent flexible display devices; and removing the layer of flexible display devices from the support plate after the etching process so as to obtain a plurality of flexible display devices separated from each other.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 16, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shuai Zhang, Yueping Zuo, Libin Liu
  • Patent number: 11177262
    Abstract: A novel semiconductor device is provided. Alternatively a memory device which can retain more multi-level data is provided. One of a source or a drain of a write transistor is electrically connected to a bit line, and the other of the source or the drain of the write transistor is electrically connected to a data retaining portion. Data written to the data retaining portion is provided to the data retaining portion through a write bit line and the write transistor. Rising of a threshold voltage which is caused in a write operation can be inhibited and more multi-level data can be retained(stored) through electrically connecting a back gate of the write transistor to the write bit line.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: November 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Seiichi Yoneda
  • Patent number: 11177132
    Abstract: Methods for doping a semiconductor layer include forming a first mask on a first region of a semiconductor layer. A second region of the semiconductor layer, that is not covered by the first mask, is doped. A second mask is formed on the second region of the semiconductor layer. The first mask is etched away. The first region of the semiconductor layer is doped.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junli Wang, Romain Lallement, Ardasheir Rahman, Liying Jiang, Brent A. Anderson
  • Patent number: 11171005
    Abstract: Included are forming, on a semiconductor substrate, an insulation film having an opening section where an opening is formed, forming a first resist on the insulation film while avoiding the opening section and the semiconductor substrate exposed via the opening section, forming a first metal on the opening section, the semiconductor substrate exposed via the opening section, and the first resist by a vapor deposition method or a sputtering method, removing, by a lift-off method, the first resist and the first metal on the first resist, forming, on the insulation film, a second resist allowing the first metal to be exposed, causing the first metal to grow a second metal by an electroless plating method, and removing the second resist, where these processings are included in the listed order.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: November 9, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kohei Nishiguchi
  • Patent number: 11164885
    Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a cell electrode structure disposed on the substrate and including interlayer insulating layers and gate electrode layers that are alternately stacked, a trench penetrating the cell structure on the substrate, a charge storage structure disposed on a sidewall surface of the trench, and a channel structure disposed adjacent to the charge storage structure and extending in a direction parallel to the sidewall surface. The channel structure includes a separate hole conduction layer and an adjacent and separate electron conduction layer. A control channel layer disposed on a control dielectric layer is a portion of the electron conduction layer configured to electrically connect to the channel structure, and to the charge storage structure. A control dielectric layer and a charge barrier layer are discrete but contiguous from the control channel structure to the charge storage structure.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyangkeun Yoo, Ju Ry Song, Se Ho Lee, Jae Gil Lee
  • Patent number: 11164970
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a gate structure disposed over a substrate between a source region and a drain region. A first inter-level dielectric (ILD) layer is disposed over the substrate and the gate structure and a second ILD layer is disposed over the first ILD layer. A field plate etch stop structure is between the first ILD layer and the second ILD layer. A field plate extends from an uppermost surface of the second ILD layer to the field plate etch stop structure. A plurality of conductive contacts extend from the uppermost surface of the second ILD layer to the source region and the drain region.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Ho, Hui-Ting Lu, Pei-Lun Wang, Yu-Chang Jong, Jyun-Guan Jhou
  • Patent number: 11158687
    Abstract: An organic light emitting display device includes a substrate, a light emitting structure, a first conductive pattern, and a functional module. The substrate has an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region, and includes a first groove, which has an enlarged lower portion, formed in the peripheral region and an opening formed in the opening region. The light emitting structure is in the display region on the substrate. The first conductive pattern overlaps the first groove in the peripheral region on the substrate. The functional module is in the opening of the substrate.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: October 26, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoonsun Choi, Wonsuk Choi, Sang Hyun Jun
  • Patent number: 11158648
    Abstract: A semiconductor device includes a substrate, a fin structure, an insulating layer, a select gate, a memory gate, and a charge trapping layer. The fin structure includes a first portion and a second extend from the substrate. Each of the first portion and the second portion includes a first sidewall and a second sidewall, and the second sidewalls are between the first sidewalls. The insulating layer is disposed between the second sidewalls of the first and second portions. The select gate and the memory gate extend across the fin structure and the insulating layer. The charge trapping layer is disposed between the memory gate and the select gate, between the memory gate and the insulating layer, and between the memory gate and the fin structure, and the second sidewalls of the first and second portions are free from in contact with the charge trapping layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Shu Huang, Ming-Chyi Liu
  • Patent number: 11152375
    Abstract: Methods, apparatuses, and systems related to patterning a material over a sense line contact are described. An example method includes forming a sense line contact pattern at an angle to a sense line direction over semiconductor structures on a substrate, wherein the angle to the sense line direction is formed along a path between a sense line contact in a first sense line column and a sense line contact in a second sense line column. The example method further includes removing a portion of a mask material corresponding to the sense line contact pattern to form sense line contacts.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Byung Yoon Kim
  • Patent number: 11145696
    Abstract: A passive matrix organic light emitting diode (PMOLED) display which includes a plurality of lower electrode patterns arranged in parallel, a plurality of transparent electrode patterns arranged in parallel in a direction and being perpendicular to the lower electrode pattern, and an organic compound layer interposed between the lower electrode pattern and the transparent electrode pattern and by time-sharing control period into a display control period and a touch sensor control period for each display frame to implement image output and touch sensing; the display includes: a plurality of mutual electrode patterns provided to the vicinity of a display area defined by the lower electrode pattern and the transparent electrode pattern; a display driving circuit; a multiplexer; and a touch driving circuit connected to the lower electrode pattern or the transparent electrode pattern through the multiplexer in the touch sensor control period.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 12, 2021
    Assignee: Solomon Systech (Shenzhen) Ltd.
    Inventors: Hong Jae Jang, Hyung-Cheol Shin, Il-Hyun Yun, Wai Hon Ng, Pui Yuen Lam
  • Patent number: 11138911
    Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate includes a flexible protective layer and sub-pixel structures. The flexible protective layer includes bosses, the sub-pixel structure is provided on a top surface of the boss, the boss further includes multiple side surfaces intersecting with the top surface, and the display substrate further includes secondary sub-pixel structures provided on at least one of the multiple side surfaces.
    Type: Grant
    Filed: May 5, 2019
    Date of Patent: October 5, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hejin Wang, Ming Che Hsieh, Shanchen Kao
  • Patent number: 11127922
    Abstract: A display device includes a first substrate including a display area and a non-display area around the display area; a pad portion at an end part of the first substrate in the non-display area; a power voltage transmitting line electrically connected to the pad portion and surrounding at least part of the display area; a second substrate facing the first substrate; and a sealant between the first substrate and the second substrate and surrounding the display area. In the end part, the power voltage transmitting line includes a first portion overlapping the sealant and extending in a first direction and a second portion not overlapping the sealant, and the second portion includes a first protrusion protruded from the first portion in a second direction crossing the first direction, and a second protrusion protruded in a direction opposite to the second direction.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 21, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung Jae Lee, Han Soo Kim, Kyung Min Park
  • Patent number: 11127880
    Abstract: An optoelectronic semiconductor device and a method for producing an optoelectronic semiconductor device are disclosed. In an embodiment an optoelectronic semiconductor device includes a semiconductor body having a first region of a first conductivity type, an active region configured to generate electromagnetic radiation and a second region of a second conductivity type in a stacking direction, an electrical contact metallization arranged on a side of the second region facing away from the active region and being opaque to the electromagnetic radiation, a radiation coupling-out region surrounding the electrical contact metallization at an edge side and an absorber layer structure arranged between the electrical contact metallization and the second region.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: September 21, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Johannes Unger, Franz Eberhard, Fabian Kopp, Katharina Christoph
  • Patent number: 11127698
    Abstract: The purpose of the present invention is to provide: a conductive film; a method for producing a conductive film, which enables the achievement of a conductive film or conductive pattern having good electrical conductivity by means of light irradiation of a short period of time without being accompanied by a long-time heat treatment at high temperatures; a method for producing a field effect transistor, which uses this method for producing a conductive film; and a method for producing a wireless communication device. A method for producing a conductive film according to the present invention for the achievement of the above-described purpose comprises: a step for forming a coating film by applying a conductive paste, which contains conductive particles that have surfaces covered by elemental carbon, onto a substrate; and a step for irradiating the coating film with flashing light.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 21, 2021
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Shota Kawai, Junji Wakita, Seiichiro Murase
  • Patent number: 11101359
    Abstract: A method of manufacturing a device includes forming a plurality of stacks of alternating layers on a substrate, constructing a plurality of nanosheets from the plurality of stacks of alternating layers, and forming a plurality of gate dielectrics over the plurality of nanosheets, respectively. The method allows for the modulation of nanosheet width, thickness, spacing, and stack number and can be employed on single substrates. This design flexibility provides for design optimization over a wide tuning range of circuit performance and power usage.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shien-Yang Wu, Ta-Chun Lin, Kuo-Hua Pan
  • Patent number: 11101404
    Abstract: A method for manufacturing a semiconductor device includes: preparing a wafer including sapphire, the wafer having an upper surface that includes a first region and a second region, the second region surrounding the first region and located at a position at least 2 ?m higher or lower than the first region; and forming a semiconductor layer at the upper surface, the semiconductor layer including at least one layer that comprises AlzGa1?zN (0.03?z?0.15).
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 24, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Yoshinori Miyamoto, Tokutaro Okabe, Yuya Kagoshima, Keisuke Higashitani, Chiaki Ozaki