Abstract: A display device and manufacturing method thereof with a high level of reliability is provided without increasing the number of manufacturing processes. The display device includes a first conductor, a first insulation layer including a first contact hole exposing a part of the first conductor, a second insulation layer including a second contact hole exposing at least a part of the first contact hole and a part of a surface of the first insulation layer, a pixel electrode overlapping a part of the second contact hole and electrically connected to the first conductor, and a third insulation layer contacting the first insulation layer via the second contact hole.

Abstract: An electrical connection structure is provided. The electrical connection structure includes a through hole, a first pad, a second pad and a conductive bridge. The through hole has a first end and a second end. The first pad at least partially surrounds the first end of the through hole and is electrically connected to a first circuit. The second pad is located at the second end of the through hole and is electrically connected to a second circuit. The conductive bridge is connected to the first pad and second pad through the through hole, thereby making the first and second circuits electrically connected to each other.

Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

Abstract: A light emitting device including a light emitting structure including a plurality of light emitting parts, a dielectric structure disposed outside the light emitting structure, and a plurality of pads disposed on a first surface of the light emitting structure and electrically coupled with the light emitting parts, in which outer sidewalls of the pads are disposed inside an outer sidewall of the light emitting structure and an outer sidewall of the dielectric structure, at least one of the pads extends to a first surface of the dielectric structure, and the first surface of the dielectric structure is coplanar with the first surface of the light emitting structure.

Abstract: Methods and systems for crystallizing a thin film provide a laser beam spot that is continually advanced across tire thin film to create a sustained complete or partial molten zone that is translated across the thin film, and crystallizes to form uniform, small-grained crystalline structures or grains.

Abstract: An electronic component built-in wiring board includes a substrate having a cavity, an electronic component accommodated in the cavity of the substrate and having pads on a surface of the component, a coating insulating layer formed on the substrate such that the insulating layer is covering the component and has via holes, via conductors formed in the via holes such that the via conductors are penetrating through the insulating layer, and a resin coating formed between the component and the insulating layer and having through holes such that the through holes are partially exposing the pads in the via holes and that the coating has adhesion to the component that is stronger than adhesion of the insulating layer to the component. The via conductors are formed in the via holes and the through holes such that the via conductors are connected to the pads on the surface of the component.

Abstract: A semiconductor device includes a semiconductor module having a wiring board, semiconductor assemblies that include a multilayer substrate on which semiconductor elements are mounted, and a sealing part; a cooler; and a heat conduction sheet which is placed between the semiconductor module and the mounting surface of the cooler and which is in contact with the bottom surfaces of the multilayer substrates. The heat conduction sheet has recesses corresponding to at least parts of the outer edges of second electrically conductive plates provided on the bottoms of the multilayer substrates.

Abstract: A power semiconductor module arrangement includes a power electronics substrate comprising a first DC voltage pad, a second DC voltage pad, a first load pad, and a second load pad, first and second transistor dies mounted on the first load pad, third and fourth transistor dies mounted the first DC voltage pad, the first and second transistor dies collectively form a first switch, the third and fourth transistor dies collectively form a second switch, the first and second DC voltage pads are arranged such that a DC supply impedance for a first commutation loop that flows through the first and third transistor dies matches a DC supply impedance for a second commutation loop that flows through the second and fourth transistor dies, and an impedance of a first load connection to the third transistor die is greater than an impedance of a second load connection to the fourth transistor die.

Abstract: A semiconductor device includes a conductive board, a contact component having a cylindrical through hole and including a main body portion with first and second open ends, and an external connection terminal inserted in the through hole of the contact component, having four outer surfaces extending in an insertion direction to form a quadrangular prism shape, and having four corner portions along an insertion direction pressed by an inner circumferential surface of the through hole of the contact component. The external connection terminal has protrusions, each of which is disposed on a respective one of at least one pair of opposite outer surfaces among the four outer surfaces, and being pressed by the inner circumferential surface of the through hole.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.

Abstract: An interconnect structure is provided. The interconnect structure includes first conducting lines and second conducting lines. The first conducting lines are formed of a first metallic material and include at least one individual first conducting line in contact with a first corresponding substrate conducting line. The second conducting lines are formed of a second metallic material and include at least one individual second conducting line between neighboring first conducting lines and in contact with a second corresponding substrate conducting line. The at least one individual second conducting line is separated from each of the neighboring first conducting lines by controlled distances.

Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

Abstract: The present disclosure provides a driving substrate and a manufacturing method thereof, and a micro LED bonding method. The driving substrate includes: a base substrate; a driving function layer provided on the base substrate, and including a plurality of driving thin film transistors and a plurality of common electrode lines; a pad layer including a plurality of pads provided on a side of the driving function layer away from the base substrate, each pad including a pad body and a microstructure of hard conductive material provided on a side of the pad body away from the base substrate; and a plurality of buffer structures provided on the side of the driving function layer away from the base substrate, each buffer structure surrounding a portion of a corresponding microstructure close to the base substrate, and a height of the buffer structure being lower than a height of the microstructure.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed over a substrate. The fin structure is sculpted to have a plurality of non-etched portions and a plurality of etched portions having a narrower width than the plurality of non-etched portions. The sculpted fin structure is oxidized so that a plurality of nanowires are formed in the plurality of non-etched portions, respectively, and the plurality of etched portions are oxidized to form oxides. The plurality of nanowires are released by removing the oxides.

Abstract: An electronic apparatus includes an integrated circuit board; a printed circuit board electrically coupled to first and second external circuits; and a ball grid array that couples the integrated circuit board and the printed circuit board, includes a first group including pieces of first ball grid, and includes a second group including pieces of second ball grid. The first group couples the first circuit block and the first external circuit. The second group couples the second circuit block and the second external circuit. The number of the pieces of first ball grid is larger than the number of the pieces of second ball grid. The minimum distance between the first group and the first side is shorter than the minimum distance between the group and the first side and is shorter than the minimum distance between the second group and the second side.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: An epitaxial growth process, referred to as metal-semiconductor junction assisted epitaxy, of ultrawide bandgap aluminum gallium nitride (AlGaN) is disclosed. The epitaxy of AlGaN is performed in metal-rich (e.g., Ga-rich) conditions using plasma-assisted molecular beam epitaxy. The excess Ga layer leads to the formation of a metal-semiconductor junction during the epitaxy of magnesium (Mg)-doped AlGaN, which pins the Fermi level away from the valence band at the growth front. The Fermi level position is decoupled from Mg-dopant incorporation; that is, the surface band bending allows the formation of a nearly n-type growth front despite p-type dopant incorporation. With controlled tuning of the Fermi level by an in-situ metal-semiconductor junction during epitaxy, efficient p-type conduction can be achieved for large bandgap AlGaN.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a channel structure extending in a direction perpendicular to the substrate; a charge storage structure disposed to be in contact with the channel structure; and a cell electrode structure disposed to be in contact with the charge storage structure in a lateral direction, wherein the channel structure comprises a hole conduction layer and an electron conduction layer.

Abstract: Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.