Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

Abstract: A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.

Abstract: System and methods for processing a substrate using a reactor with multiple heating zones and control of said heating zones using a common terminal shared between two power supplies are provided. The reactor includes a heater assembly for supporting the substrate and a showerhead for supplying process gases into the reactor. An inner heater and an outer heater are integrated in the heater assembly. An inner power supply has a positive terminal connected to a first end of the inner heater and a negative terminal is connected to a second end of the inner heater that is coupled to a common terminal. An outer power supply has a positive terminal connected to a first end of the outer heater and a negative terminal connected to a second end of the outer heater that is coupled to the common terminal. A common-terminal heater module is configured to receive a measured temperature that is proximate to the inner heater.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: A method for depositing a Group IV semiconductor is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The methods may further include, exposing the substrate to at least one Group IV precursor and exposing the substrate to at least one Group IIIA metalorganic dopant precursor. The methods may further include depositing a Group IV semiconductor on a surface of the substrate. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.

Abstract: A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.

Abstract: A semiconductor device includes a semiconductor package equipped with a plurality of electrodes and a mount member which is equipped with a plurality of lands and on which the semiconductor package is mounted. The semiconductor package has the electrodes joined to the lands through solders. One of the electrodes is designed as a position/orientation control electrode for the semiconductor package. One of the lands is designed as a position/orientation control land for the semiconductor package. The position/orientation control land is arranged inside the position/orientation control electrode in a planar view thereof and includes a plurality of first extensions which extend in different radial directions about the center of the semiconductor package. The position/orientation control electrode includes a plurality of second extensions which extend along the first extensions. Each of the first extension has an outer portion which is located outside an outer line of a facing one of the second extensions.

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

Abstract: A semiconductor structure includes a base substrate including a first region and a second region. The semiconductor further includes a first fin member located over the first region, a second fin member located over the second region, a first dummy gate across a surface of the first fin member, and a second dummy gate across a surface of the second fin member. A first opening is formed in the first fin member located on each side of the first dummy gate, a second opening is formed between two adjacent first channel layers, a third opening is formed in the second fin member located at each side of the second dummy gate, and a fourth opening is formed between two second channel layers. The semiconductor structure still further includes a first inner spacer located in the second opening, and a second inner spacer located in the fourth opening.

Abstract: A display panel includes a substrate, a thin-film transistor layer disposed on the substrate, an auxiliary layer disposed between the substrate and the thin-film transistor layer and including a first auxiliary layer and at least a second auxiliary layer disposed on a side of the first auxiliary layer close to the substrate. A dielectric constant of a constituent material of the first auxiliary layer is less than a dielectric constant of a constituent material of the substrate and is greater than a dielectric constant of a constituent material of the second auxiliary layer. The second auxiliary layer includes a plurality of auxiliary portions arranged at intervals.

Abstract: A method for manufacturing a semiconductor device includes forming an N-type layer on the first surface of the N+ type substrate, etching the N-type layer to form a trench, forming a sacrificial layer on an inner bottom surface of the trench, forming a first mask on an inner side of the trench, removing the sacrificial layer, and forming a P type shield region by implanting ions into an inner surface of the trench exposed by the removal of the sacrificial layer.

Abstract: A package structure includes a thermal dissipation structure, a first encapsulant, a die, a through integrated fan-out via (TIV), a second encapsulant, and a redistribution layer (RDL) structure. The thermal dissipation structure includes a substrate and a first conductive pad disposed over the substrate. The first encapsulant laterally encapsulates the thermal dissipation structure. The die is disposed on the thermal dissipation structure. The TIV lands on the first conductive pad of the thermal dissipation structure and is laterally aside the die. The second encapsulant laterally encapsulates the die and the TIV. The RDL structure is disposed on the die and the second encapsulant.

Abstract: A semiconductor package device, a wearable device, and a temperature detection method are provided. The semiconductor package includes a substrate, an optical module, and a temperature module. The optical module is disposed on the substrate. The temperature module is disposed on the substrate and adjacent to the optical module. The temperature module comprises a semiconductor element and a temperature sensor stacked on the semiconductor element. The optical module is configured to detect a distance between the optical module and an object.

Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.

Abstract: A semiconductor device comprises a semiconductor chip comprising a radio frequency (RF) circuit, a feedline structure coupled to the RF circuit, and an antenna structure comprising a main body stretching along a direction orthogonal to at least one side of a front side and a backside of the semiconductor device, wherein the antenna structure is coupled to the RF circuit through the feedline structure.

Abstract: A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

Abstract: An electronic component module includes a substrate, a connector, an electronic component, a conductor wall, an insulating resin, and a conductive shield film. The connector and the electronic component are mounted on a first main surface of the substrate. The conductor wall has a cylindrical shape, is mounted on the first main surface of the substrate, and includes an interior space in which the connector is disposed. The insulating resin is provided on the first main surface. The conductive shield film is provided on a surface of the insulating resin. The insulating resin covers the electronic component and is disposed outside the conductor wall except the interior space of the conductor wall.

Abstract: A manufacturing method includes depositing a chamber protective layer in a chamber, supplying a first purge gas to the chamber, transferring a substrate to the chamber, the substrate being disposed inside an edge ring on an electrostatic chuck, processing the substrate, supplying a second purge gas to the chamber, transferring the substrate to an outside of the chamber, removing the chamber protective layer, and supplying a third purge gas to the chamber. Variation of the surface roughness of the edge ring may be minimal. A ratio of an edge gas flow rate of gas supplied to an edge of the substrate and the edge ring to a central gas flow rate of gas supplied to a central portion of the substrate in the processing the substrate may be 0.05 to 19. The flow rate ratio may be more than 1 in the supplying the second purge gas.

Abstract: An electronic apparatus includes: a circuit board; a driving chip mounted on the circuit board; a shield-can including a top surface and a side surface extending in a direction from the top surface to the circuit board, wherein the top surface covers the driving chip; and a first film disposed on the shield-can and including a first opening that exposes a part of the top surface of the shield-can.

Abstract: A semiconductor package includes a printed circuit board (PCB), a semiconductor device, an interposer, and a conductive adhesive. The PCB has a top surface with at least one ground area formed thereon. The semiconductor device has a bottom surface with at least one first first-type contact formed thereon. The interposer is located between the semiconductor device and the PCB. The bottom surface of the semiconductor device is adhered to a top surface of the interposer by the conductive adhesive. The conductive adhesive overflows from an edge of the top surface of the interposer to have contact with the at least one ground area on the top surface of the PCB.