Abstract: A heat radiation member for a flexible display having a bending panel fixing member is disclosed, and an electronic device using the same is disclosed, wherein the heat radiation member includes a heat radiation sheet portion including a metal layer; a bending panel fixing member attached to a first area in one surface of the heat radiation sheet portion; a spacer attached to a second area in the one surface of the heat radiation sheet portion; a dummy double sided tape attached to the spacer; an upper delamination film covering an entire area of the other surface of the heat radiation sheet portion; and a lower delamination film covering an entire area of the dummy double sided tape and an entire area of the bending panel fixing member.

Abstract: A light emitting device, includes: a substrate; a light emitting element on the substrate, the light emitting element having a first end portion and a second end portion arranged in a longitudinal direction; one or more partition walls disposed on the substrate, the one or more partition walls being spaced apart from the light emitting element; a first reflection electrode adjacent the first end portion of the light emitting element; a second reflection electrode adjacent the second end portion of the light emitting element; a first contact electrode connected to the first reflection electrode and the first end portion of the light emitting element; an insulating layer on the first contact electrode, the insulating layer having an opening exposing the second end portion of the light emitting element and the second reflection electrode to the outside; and a second contact electrode on the insulating layer.

Abstract: A display device is disclosed. In one aspect, the device includes a substrate and a display unit disposed on the substrate and including a plurality of pixels each pixel including a thin film transistor, a display element electrically connected to the thin film transistor, and a planarization layer interposed between the thin film transistor and the display element. The display unit includes a display region and a non-display region surrounding the display region, wherein the non-display region includes a voltage line. The planarization layer comprises a central portion, an outer portion and a dividing region interposed between the central and outer portions, wherein the dividing region is located in the non-display region. The planarization layer covers at least a lateral side of the voltage line formed in the dividing region.

Abstract: A system for monitoring one or more conditions of an automation system of a semiconductor factory includes one or more instrumented substrates, one or more sealable containers and one or more system servers. The one or more instrumented substrates include one or more sensors. The one or more sensors measure one or more conditions of the one or more instrumented substrates as the one or more sealable containers transport the one or more instrumented substrates through the semiconductor factory. The one or more sealable containers also receive sensor data from the one or more sensors included on the one or more instrumented substrates. The one or more system servers are configured to receive the sensor data from the one or more sealable containers. The one or more servers are configured to identify one or more deviations in the measured one or more conditions.

Abstract: The present application describes a display panel having a plurality of subpixels. Each of the plurality of subpixels has a light blocking region and a light transmissive region surrounding the light blocking region. Each of the plurality of subpixels in the light blocking region includes a first base substrate and a second base substrate facing each other; a first light emitting element and a first reflective block on a side of the first base substrate proximal to the second base substrate; and a second reflective block on a side of the second base substrate proximal to the first base substrate. The first reflective block and the second reflective block are configured to reflect light emitted from the first light emitting element to the light transmissive region thereby displaying an image.

Abstract: Disclosed is a conversion element (1) comprising an active region (13) that is formed by a semiconductor material and includes a plurality of barriers (131) and quantum troughs (132), a plurality of first structural elements (14) on a top face (la) of the conversion element (1), and a plurality of second structural elements (15) and/or third structural elements (16) which are arranged on a face of the active region (13) facing away from the plurality of first structural elements (14). Also disclosed is a method for producing a conversion element of said type.

Abstract: An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes a semiconductor chip including a plurality of pixels, each pixel configured to emit electromagnetic primary radiation from a radiation exit surface and conversion layers located on at least a part of the radiation exit surfaces, wherein the conversion layers comprise a crosslinked matrix having a three-dimensional siloxane-based network and at least one phosphor embedded in the matrix, and wherein the conversion layers have a thickness of ?30 ?m.

Abstract: A method is disclosed herein. The method includes dicing a wafer and applying a mask. The method includes spraying die bond material, at a first temperature, to a surface of the wafer and cooling the die bond material at a second temperature to at least partially solidify the die bond material. The method also includes removing the mask from the wafer through the die bond material. After the removing of the mask, the method includes curing the die bond material to form a die attach film layer on the wafer.

Abstract: A solar cell module is discussed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate and a plurality of first electrodes and a plurality of second electrodes, which are formed on a back surface of the semiconductor substrate and are separated from each other, the plurality of solar cells disposed in a first direction; a plurality of first conductive lines connected to the plurality of first electrodes included in a first solar cell of the plurality of solar cells, and the plurality of first conductive lines extended in the first direction; a plurality of second conductive lines connected to the plurality of second electrodes included in a second solar cell of the plurality of solar cells which is adjacent to the first solar cell, and the plurality of second conductive lines extended in the first direction.

Abstract: A half bridge power module (1) comprising a substrate (2) comprising an inner load track (11), two intermediate load tracks (12, 14) and two outer load tracks (10,13), wherein an external terminal is mounted on one of the intermediate load tracks (12, 14), an external terminal (3, 4) is mounted on one of the outer load tracks (10, 13) and an external terminal (5) is mounted on the inner load track (11); wherein semiconductor switches (101, 12, 105, 106) are mounted on the outer load tracks (10, 13) and are electrically connected to the intermediate load track (12); and semiconductor switches (103, 104, 107, 108) are mounted on the intermediate load tracks (12, 14) and are electrically connected to the inner load track (11).

Abstract: An electronic package is provided and uses a plurality of bonding wires as a shielding structure. The bonding wires are stitch bonded onto a carrier carrying electronic components, such that the problem of the shielding structure peeling off or falling off from the carrier can be avoided due to the fact that the bonding wires are not affected by temperature, humidity and other environmental factors.

Abstract: According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.

Abstract: The present disclosure relates to a semiconductor package that may include a substrate, an interposer coupled to the substrate, a shield frame including at least one frame recess and at least one opening positioned over the interposer, a conductive shield layer on the shield frame, and a plurality of components coupled to the interposer.

Abstract: The present invention provides a display panel and a manufacturing method thereof. The display panel includes a glass substrate and a one-dimensional photonic crystal layer disposed on the glass substrate. The one-dimensional photonic crystal layer includes a plurality of crystal unit layers stacked upon each other. Each of the plurality of crystal unit layers includes a low-refractive-index sublayer disposed on a side of each of the plurality of crystal unit layers near the glass substrate and a high-refractive-index sublayer disposed on a side of each of the plurality of crystal unit layers away from the glass substrate.

Abstract: A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

Abstract: Semiconductor structures involving multiple quantum wells provide increased efficiency of UV and visible light emitting diodes (LEDs) and other emitter devices, particularly at high driving current. LEDs made with the new designs have reduced efficiency droop under high current injection and increased overall external quantum efficiency. The active region of the devices includes separation layers configured between the well layers, the one or more separation regions being configured to have a first mode to act as one or more barrier regions separating a plurality of carriers in a quantum confined mode in each of the quantum wells being provided on each side of the one or more separation layers and a second mode to cause spreading of the plurality of carriers across each of the quantum wells to increase an overlap integral of all of the plurality of carriers. The devices and methods of the invention provide improved efficiency for solid state lighting, including high efficiency ultraviolet LEDs.

Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.

Abstract: The present invention provides a semiconductor device for reducing parasitic inductance. The semiconductor device of the present invention includes: a semiconductor chip, including a front surface and a hack surface, and including a source pad, a drain pad and a gate pad on the front surface; a die pad, disposed under the semiconductor chip and bonded to the hack surface of the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin, sealing the semiconductor chip, the die pad and each of the leads. At least one via for external connection is formed in the semiconductor chip to connect to the source pad, and the via for external connection is disposed on a circumferential portion of the semiconductor chip in perspective view.

Abstract: An electronic component includes a substrate comprising a die attach region and a perimeter region on a front side of the substrate; and at least one thermal indicator disposed within the perimeter region for monitoring the cumulative heat exposure of the substrate. The thermal indicator signals when the predetermined thermal budget limit that correlates with the decline in the condition of the OSP layer or the degradation of the adhesion of the die attach films is reached.

Abstract: Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.