Abstract: A manufacturing method for a semiconductor apparatus sequentially includes bonding a first chip and a second chip together using an adhesive. The first chip includes a first electrode and has a protrusion, and the second chip has a recess. In the bonding, the first chip and the second chip are bonded together in such a manner that the protrusion is positioned into the recess. Further, the method includes forming a through hole in the second chip to expose the first electrode, the first surface being opposite to a second surface having the recess, and forming the second electrode which is electrically connected to the first electrode, in the through hole.

Abstract: A package structure including a first die, an encapsulant, a first circuit structure, a second circuit structure, a conductive connector, a second die, and a filler is provided. The encapsulant covers the first die and has a first surface and a second surface opposite to each other. The first circuit structure is disposed on the first surface. The second circuit structure is disposed on the second surface. The conductive connector penetrates the encapsulant. The second die is disposed on the second circuit structure. The second die has an optical signal transmission area. The filler is disposed between the second die and the second circuit structure. An upper surface of the second circuit structure has a groove. The upper surface includes a first area and a second area disposed on opposite sides of the groove. The filler directly contacts the first area. The filler is disposed away from the second area.

Abstract: A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate in a first direction, a first metal layer on the first substrate, a second metal layer on the first substrate and spaced apart from the first metal layer in a second direction, a first semiconductor element, and a second semiconductor element. The second substrate includes a main wiring and a signal wiring. The first semiconductor element includes a first electrode on the first metal layer, a second electrode connected to the main wiring, and a first gate electrode connected to the signal wiring. The second semiconductor element includes a third electrode on the second metal layer, a fourth electrode connected to the main wiring, and a second gate electrode connected to the signal wiring. During operation, current flows in wiring layers of the main wiring in opposite directions.

Abstract: A semiconductor device, including a semiconductor module and a conducting board. The semiconductor module includes a semiconductor chip and an external connecting terminal which has a first end electrically connected to the semiconductor chip and a second end extending from the semiconductor chip. The conducting board has a terminal hole penetrating therethrough, an inlet and an outlet of the terminal hole being respectively on two opposite surfaces of the conducting board. The conducting board is electrically connected to the external connecting terminal, of which the second end fits into the terminal hole from the inlet toward the outlet, and is fixed therein by solder. At least one of the terminal hole and the second end of the external connecting terminal has a lock part. The second end of the external connecting terminal, inserted into the terminal hole, is locked by the lock part and thereby remains in the terminal hole.

Abstract: An electronic apparatus includes: a circuit board; a driving chip mounted on the circuit board; a shield-can including a top surface and a side surface extending in a direction from the top surface to the circuit board, wherein the top surface covers the driving chip; and a first film disposed on the shield-can and including a first opening that exposes a part of the top surface of the shield-can.

Abstract: A module includes: a substrate including a first main surface; a first component mounted on the first main surface; a first land electrode provided on the first main surface; a first mold resin that covers at least the first main surface and the first component; a top surface shield film that covers a top surface of the first mold resin; a side surface shield film that covers a side surface of the first mold resin; a first conductor pillar provided in the first mold resin to electrically connect the first land electrode and the top surface shield film; and an upper first bypass conductor provided in the first mold resin to electrically connect the top surface shield film and the side surface shield film.

Abstract: A semiconductor module includes a multilayer substrate having a main wiring layer formed therein, a main current flowing in the main wiring layer when the semiconductor device is turned on, a first and second semiconductor elements, each of which has a top electrode on a top surface thereof and a bottom electrode on a bottom surface thereof, and is disposed on a top surface of the main wiring layer to which the bottom electrode is conductively connected, a metal plate having an end portion, a bottom surface of the end portion being conductively connected to the top electrode of the first semiconductor element, and a control board including an insulating plate disposed on the top surface of the end portion and a control wiring layer disposed on a top surface of the insulating plate for controlling turning on and off of the first and second semiconductor elements.

Abstract: A semiconductor package includes a first package substrate; a first semiconductor chip on the first package substrate; a first conductive connector on the first package substrate; and an interposer including a central portion on the first semiconductor chip and an outer portion having the first conductive connector attached thereto. The central portion of the interposer includes a bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate. A thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer.

Abstract: An apparatus is provided which comprises: a plurality of interconnects to couple a silicon interposer to a substrate; and a landing pad configured in a non-circle shape, wherein the plurality of interconnects are adjacent to the landing pad at one end of the plurality of interconnects through a plurality of vias.

Abstract: An apparatus includes a biosensor integrated circuit (IC) chip having multiple well structures configured to receive a liquid comprising one or more biological analytes. The well structures include a passivation layer with an opening over one or more field effect transistors (gFETs) which include a layer of 2D channel material selected from molybdenum disulfide (MoS2) and graphene; a drain electrode connected to a first end of the channel; a source electrode connected to a second end of the channel, wherein the individual gFETs are configured such that liquid received by the well structure is confined to form a liquid gate above a top surface of the channel. A system and method perform various functions of the apparatus.

Abstract: A fan-out type semiconductor package includes: a frame including a cavity and a middle redistribution layer (RDL) structure at least partially surrounding the cavity; a semiconductor chip in the cavity; a lower RDL structure on the frame and electrically connected with the semiconductor chip and the middle RDL structure; an upper RDL structure on the frame and electrically connected with the middle RDL structure; an upper shielding pattern in the upper RDL structure to shield the semiconductor chip from electromagnetic interference (EMI); a lower shielding pattern in the lower RDL structure to shield the semiconductor chip from the EMI; and a side shielding pattern in the middle RDL structure to shield the semiconductor chip from the EMI. The upper shielding pattern and the lower shielding pattern have a thickness of no less than about 5 ?m, and the side shielding pattern has a width of no less than about 5 ?m.

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

Abstract: An electronic component package has an outer edge including a first side and a second side adjacent to each other. The electronic component package includes a first electronic component chip, a second electronic component chip provided at a distance from the first electronic component chip, one or more first terminals disposed along the first side, one or more second terminals disposed along the second side, and one or more first conductors. The one or more first conductors couple the one or more first terminals to the first electronic component chip, with the one or more first terminals being uncoupled to the second electronic component chip.

Abstract: A luminescence device includes a first electrode, a first emission portion disposed on the first electrode, a second electrode disposed on the first emission portion, and a capping layer disposed on the second electrode and including a metal atom and a metal halide compound, wherein the metal atom is a lanthanide metal, a transition metal, or a post-transition metal and the metal halide compound is formed by combining an alkali metal atom and a halogen atom.

Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.

Abstract: A method of processing a power diode includes: creating an anode region and a drift region in a semiconductor body; and forming, by a single ion implantation processing step, each of an anode contact zone and an anode damage zone in the anode region. Power diodes manufactured by the method are also described.

Abstract: A wiring board includes a first wiring layer, a high-speed wiring disposed in the first wiring layer, a second wiring layer, and a signal wiring disposed in the second wiring layer. The signal wiring transmits a signal slower than that through the high-speed wiring. A third wiring layer between the first and second wiring layers includes a power supply wiring and/or a ground wiring, which is not disposed in a portion where a land of the first wiring layer and the signal wiring do not overlap. The power supply wiring and/or the ground wiring overlap the signal wiring in a portion where the land of the first wiring layer and the signal wiring overlap each other.

Abstract: A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 ?m and less than 200 ?m. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 ?m and 800 ?m.

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

Abstract: A semiconductor package includes a package substrate, a lower chip, an interposer, and an upper chip which are stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes first and second lower chip pads spaced apart from each other on an upper surface of the lower chip, wire bonding pads bonded to the bonding wires on the upper surface of the lower chip, and lower chip redistribution lines electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through via electrode electrically connecting the upper chip connection pad to the lower chip connection pad.