Abstract: An organic light emitting display device includes a substrate, a light emitting structure, a first conductive pattern, and a functional module. The substrate has an opening region, a peripheral region surrounding the opening region, and a display region surrounding the peripheral region, and includes a first groove, which has an enlarged lower portion, formed in the peripheral region and an opening formed in the opening region. The light emitting structure is in the display region on the substrate. The first conductive pattern overlaps the first groove in the peripheral region on the substrate. The functional module is in the opening of the substrate.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

Abstract: An electronic device package is provided. The electronic device package includes a redistribution layer (RDL), a first electronic component and an interconnector. The RDL includes a topmost circuit layer, and the topmost circuit layer includes a conductive trace. The first electronic component is disposed over the RDL. The interconnector is disposed between the RDL and the first electronic component. A direction is defined by extending from a center of the first electronic component toward an edge of the first electronic component, and the direction penetrates a first sidewall and a second sidewall of the interconnector, the second sidewall is farther from the center of the first electronic component than the first sidewall is, and the conductive trace is outside a projection region of the second sidewall.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes etching a dummy gate to form a gate trench to expose a channel portion of a first fin and a first isolation structure; depositing a gate dielectric layer and first and second work function layers, wherein the second work function layer has a first portion directly over the channel portion of the first fin and a second portion directly over the first isolation structure; etching the second portion of the second work function layer, wherein the first portion of the second work function layer remains; depositing a third work function layer over and in contact with the first portion of the second work function layer and the first work function layer; and filling the gate trench with a gate metal.

Abstract: A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.

Abstract: A display device includes a light emitting element layer including a plurality of light emitting elements configured to output first color light, a color conversion layer on the light emitting element layer to receive the first color light, the color conversion layer being configured to convert the first color light so as to output at least two lights having colors different from each other, and a light collection layer between the light emitting element layer and the color conversion layer to collect the first color light, thereby providing the collected first color light to the color conversion layer. The light collection layer that collects the first color light may be disposed between the color conversion layer and the light emitting element layer to improve the light efficiency of the first color light outputted from the light emitting element layer, and also to prevent (or reduce) the colors from being mixed between the pixel areas, thereby improving the display quality.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate, a first module disposed on the substrate, a second module disposed on the substrate and spaced apart from the first module, and a conductive element disposed outside of the substrate and configured to provide a signal transmission path between the first module and the second module.

Abstract: The circuit board includes a plurality of bonding pads having a first bonding pad and a second bonding pad configured to supply a ground potential; a first ground wiring connected to the first bonding pad; a second ground wiring connected to the second bonding pad; and a first extension pad connected to the first ground wiring and a second extension pad connected to the second ground wiring, the first extension pad and the and second extension pad being provided in a different area from an area in which the plurality of bonding pads is provided, the first extension pad and the and second extension pad being connectable through a wire.

Abstract: A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin formed from a material having a coefficient of thermal expansion similar to a coefficient of thermal expansion of the encapsulation resin. The covering resin is disposed on the upper surface of the upper substrate and covers a side surface of the wiring layer.

Abstract: A semiconductor device comprises a semiconductor chip comprising a radio frequency (RF) circuit, a feedline structure coupled to the RF circuit, and an antenna structure comprising a main body stretching along a direction orthogonal to at least one side of a front side and a backside of the semiconductor device, wherein the antenna structure is coupled to the RF circuit through the feedline structure.

Abstract: A package structure includes a redistribution structure and a core substrate. The redistribution structure includes a plurality of connection pads. The core substrate is disposed on the redistribution structure and electrically connected to the plurality of connection pads. The core substrate includes a first interconnection layer and a plurality of conductive terminals. The first interconnection layer has a first region, a second region surrounding the first region, and a third region surrounding the second region, and includes a plurality of bonding pads located in the first region, the second region and the third region. The conductive terminals are electrically connecting the plurality of bonding pads to the plurality of connection pads of the redistribution structure, wherein the plurality of conductive terminals located over the first region, the second region and the third region of the first interconnection layer have different heights.

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

Abstract: A resist underlayer film-forming composition exhibiting high etching resistance, high heat resistance, and excellent coatability; a resist underlayer film obtained using the resist underlayer film-forming composition and a method for producing the same; a method for forming a resist pattern; and a method for producing a semiconductor device. A resist underlayer film-forming composition including a polymer and a compound represented by Formula (1) as a solvent. In Formula (1), R1, R2, and R3 in Formula (1) each independently represent a hydrogen atom or an alkyl group having 1 to 20 carbon atoms, which may be interrupted by an oxygen atom, a sulfur atom, or an amide bond, and R1, R2, and R3 may be the same or different and may bond to each other to form a ring structure.

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

Abstract: The present disclosure relates to a package capable of handling high radio frequency (RF) power, which includes a carrier, a ring structure attached to a top surface of the carrier, an RF die attached to the top surface of the carrier within an opening of the ring structure and electrically connected to the ring structure, a heat spreader attached to a top surface of the ring structure, and an output signal lead configured to send out RF output signals generated by the RF die. Herein, the heat spreader covers a portion of the top surface of the ring structure at an output side of the package, and the output signal lead is attached to a top surface of the heat spreader. As such, the RF output signals are capable of being transmitted from the RF die to the output signal lead through the ring structure and the heat spreader.

Abstract: Semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (SoIS) package. The SoIS package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. The integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. In some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. The integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures. The SoIS package may also include an interposer connected to the integrated fan out structure for external connection to the SoIS package.

Abstract: An electronic module has a first substrate 11; a first electronic element 13 provided on one side of the first substrate 11; a first connection body 60 provided on the one side of the first electronic element 13; a second electronic element 23 provided on the one side of the first connection body 60; and a second connection body 70 provided on the one side of the second electronic element 23. The first electronic element 13 and the second electronic element 23 do not overlap in a plane direction.

Abstract: A transistor having a vertical structure can include a substrate, a first electrode disposed on the substrate, a second electrode disposed on the substrate, an insulation pattern disposed between the first electrode and the second electrode, an active layer connected between the first electrode and the second electrode, a channel area of the active layer disposed along a side surface of the insulation pattern and around an upper edge of the insulation pattern, a gate electrode disposed on the active layer, and a gate insulating film disposed between the gate electrode and the active layer.

Abstract: The present disclosure provides an electronic package and method of manufacturing the same. The electronic package includes an electronic device including a first carrier and a first electronic component disposed on the first carrier, a second carrier adjacent to the first carrier of the electronic device, and a conductive layer at least partially covering the electronic device, and separating the electronic device from the second carrier.