Patents Examined by Michele Fan
  • Patent number: 11677018
    Abstract: A semiconductor device includes a substrate, a circuit element disposed on or above the upper surface of the substrate, an electrode disposed on or above the upper surface of the substrate and connected to the circuit element, and a conductor pillar bump for external connection which is disposed on the substrate and electrically connected to the electrode or the circuit element. The substrate includes a first base and a second base disposed on the first base. The circuit element and the electrode are disposed on the second base. The first base has lower thermal resistance than the second base.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: June 13, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Masayuki Aoike
  • Patent number: 11672143
    Abstract: An organic light emitting diode display device includes a substrate, a first pixel structure, a second pixel structure, a thin film encapsulation structure, and a functional module. The substrate includes a display region and a module region. The display region includes a first pixel region, and the module region includes a second pixel region and a transmissive region. The first pixel structure is disposed in the first pixel region on the substrate. The second pixel structure is disposed in the second pixel region on the substrate. The thin film encapsulation structure is disposed on the first and second pixel structures, and includes a plurality of scatterers in the first module region. The functional module is disposed in the module region on a bottom surface of the substrate.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: June 6, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kyung Hyun Choi, Jin Koo Chung
  • Patent number: 11664314
    Abstract: A foundation portion and a conductive base portion disposed on the foundation portion are formed on a temporary support, a semiconductor element electrically connected to the base portion is disposed on a side of the temporary support on which the foundation portion and the base portion are formed, and an insulating layer coming into a state of burying the foundation portion, the base portion, and the semiconductor element is formed on the temporary support. Subsequently, surfaces of the foundation portion and the insulating layer on a side of the temporary support are exposed by removing the temporary support, and the exposed foundation portion is further removed, thereby disposing the base portion in a state of being more recessed than the surface of the insulating layer. An external connection terminal is formed on the exposed base portion to manufacture the semiconductor package.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: May 30, 2023
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Masanori Shindo
  • Patent number: 11665926
    Abstract: A display device includes a display region in which a plurality of pixels are arranged two-dimensionally. Each of the plurality of pixels includes a light-emitting layer and an optical member that refracts light from the light-emitting layer. In an orthographic projection of a first optical member included in a first pixel with respect to the light-emitting layer, a position of an apex of the first optical member and a position of a center of the first optical member are separated by a first distance.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 30, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yojiro Matsuda, Hidekazu Takahashi, Yoshihito Harada
  • Patent number: 11664299
    Abstract: A mounting board includes an electrode pad and an insulating protective film on an insulating resin layer. In a plan view, the electrode pad includes first and second sides running parallel in a first direction. The insulating protective film includes an opening including first and second regions adjoining each other in the first direction. The first region lies over the electrode pad to expose part of the electrode pad. The second region exposes part of the insulating resin layer. The first region is defined by third and fourth sides that are between the first and second sides in a second direction perpendicular to the first direction and run parallel in the first direction. The maximum dimension of the second region in the second direction is greater than the distance between respective ends of the third and fourth sides at which the first region adjoins the second region.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: May 30, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Seiichi Shimada
  • Patent number: 11664357
    Abstract: Techniques for joining dissimilar materials in microelectronics are provided. Example techniques direct-bond dissimilar materials at an ambient room temperature, using a thin oxide, carbide, nitride, carbonitride, or oxynitride intermediary with a thickness between 100-1000 nanometers. The intermediary may comprise silicon. The dissimilar materials may have significantly different coefficients of thermal expansion (CTEs) and/or significantly different crystal-lattice unit cell geometries or dimensions, conventionally resulting in too much strain to make direct-bonding feasible. A curing period at ambient room temperature after the direct bonding of dissimilar materials allows direct bonds to strengthen by over 200%. A relatively low temperature anneal applied slowly at a rate of 1° C. temperature increase per minute, or less, further strengthens and consolidates the direct bonds.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 30, 2023
    Assignee: Adeia Semiconductor Bonding Technologies Inc.
    Inventors: Gaius Gillman Fountain, Jr., Chandrasekhar Mandalapu, Laura Wills Mirkarimi
  • Patent number: 11658109
    Abstract: An electronic module has a first substrate 11, a first electronic element 13, a second electronic element 23, a second substrate 21, a first terminal part 110 provided on a side of the first substrate 11 and a second terminal part 120 provided on a side of the second substrate 21. The first terminal part 110 has a first surface direction extending part 114 and a first normal direction extending part 113 extending toward one side or the other side. The second terminal part 120 has a second surface direction extending part 124 and a second normal direction extending part 123 extending toward one side or the other side. The second surface direction extending part 124 is provided on one side of the first surface direction extending part 114, and the first surface direction extending part 114 and the second surface direction extending part 124 overlap one another in a surface direction.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: May 23, 2023
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Kosuke Ikeda, Osamu Matsuzaki
  • Patent number: 11658102
    Abstract: A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than ?20 dB.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: May 23, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuanhao Yu, Cheng Yuan Chen, Chun Chen Chen, Jiming Li, Chien-Wen Tu
  • Patent number: 11659728
    Abstract: Disclosed are a display panel, a manufacturing method thereof and a display device. The display panel includes a substrate, multiple organic light emitting elements, and a film encapsulation layer. The film encapsulation layer covers more than one of the multiple organic light emitting elements, the film encapsulation layer includes a lens layer and a first cover layer, the lens layer is located on a side of the first cover layer facing the organic light emitting elements, materials of the lens layer and the first cover layer are both organic materials, a refractive index of the lens layer is M, a refractive index of the first cover layer is N, N<M, the lens layer includes multiple lenses, and a surface of each of the multiple lenses facing away from the organic light emitting elements is convex towards a side facing away from the multiple organic light emitting elements.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 23, 2023
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yong Yuan, Guofeng Zhang
  • Patent number: 11646286
    Abstract: Solder joints comprising two different solder materials having different melting points, an outer solder material extending over an inner solder material bonded to a conductive pad, the inner solder material having a lower melting point than a melting point of the outer solder material and being in a solid state at substantially ambient temperature. A metal material having a higher melting point than a melting point of either solder material may coat at least a portion of the inner solder material. Microelectronic components, assemblies and electronic systems incorporating the solder joints, as well as processes for forming and repairing the solder joints are also disclosed.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 9, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Shams U. Arifeen, Christopher Glancey, Koustav Sinha, Xiao Li
  • Patent number: 11646257
    Abstract: An electronic device module includes a first board including a first side and a second side facing in opposite directions, the first side of the first board being configured to have a first electronic device mounted thereon; a second board adhered to the second side of the first board, and including a device accommodating portion that is a space formed by removing a central portion of the second board; a second electronic device disposed in the device accommodating portion and mounted on the second side of the first board so that the second electronic device is adjacent to an internal edge side of the second board defining a boundary of the device accommodating portion; and a bonding layer disposed in a gap between the first board and the second board and extending into a gap between the second side of the first board and the second electronic device, the bonding layer bonding the second board and the second electronic device to the first board.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 9, 2023
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chulhwan Jung
  • Patent number: 11637122
    Abstract: A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: April 25, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11635539
    Abstract: Scattered body waves are isolated to primary, shear, and surface waves as a receiver wavefield from recorded near-surface scattered wave data generated by scatters. The isolated receiver wavefield is backward propagated through an earth model from a final to an initial state. A source wavefield and the receiver wavefields are cross-correlated. A source wavefield and the receiver wavefields are stacked, over all time steps and sources, to generate a subsurface image. A display of the subsurface image is initiated.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 25, 2023
    Assignee: Saudi Arabian Oil Company
    Inventor: Abdulaziz Mohammad Almuhaidib
  • Patent number: 11631645
    Abstract: A circuit module (101) includes a circuit board (1) having a main surface (1u), an electronic component (3) mounted on the main surface (1u), and a sealing resin (4) covering at least part of the electronic component (3) on the main surface (1u). A recess (7) is formed on at least part of a side surface (11) of the sealing resin (4). At least the recess (7) is covered with an electrically conductive film (6).
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 18, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Okada, Kazushige Sato, Takafumi Kanno, Nobumitsu Amachi
  • Patent number: 11626358
    Abstract: A semiconductor device, including a circuit pattern, a contact part and an external connection terminal. The contact part has a cylindrical through-hole and first and second opening ends opposite to each other, the second opening end being joined to the circuit pattern. The external connection terminal has a prismatic main body portion and first and second end portions, the second end portion being inserted into the through-hole from the first opening end of the contact part. The main body portion of the external connection terminal has an insertion prevented portion formed thereon. The contact part includes an insertion preventing portion formed on an inner circumferential surface of the through-hole, the insertion preventing portion being so positioned as to be substantially downstream, with respect to an insertion direction of the external connection terminal, from the main body portion of the external connection terminal inserted into the through-hole.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: April 11, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Rikihiro Maruyama, Seiichi Takahashi
  • Patent number: 11621243
    Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 4, 2023
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
  • Patent number: 11605714
    Abstract: A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 14, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Kak Lee, Min Woo Kim, Bong Hyun Kim, Hee Young Park, Seo Jin Ahn, Won Yong Lee
  • Patent number: 11600679
    Abstract: A display apparatus includes a first transistor, a first data line, a second data line, a driving voltage line, and a first insulating layer. The first transistor includes a first semiconductor layer and a first gate electrode. The first semiconductor layer includes a source region and a drain region. The first data line is disposed at a left side of the first transistor, and the second data line is disposed at a right side of the first transistor. The driving voltage line at least partially overlaps the first data line and the second data line. The first insulating layer is disposed between the first data line and the driving voltage line and between the second data line and the driving voltage line.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyunchol Bang, Chulkyu Kang, Jinwoo Park, Dongsun Lee, Sangmoo Choi
  • Patent number: 11600587
    Abstract: A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsien-Wei Chen
  • Patent number: 11594517
    Abstract: A semiconductor device includes a first lead, a second lead, a control element, an insulating element, and a driver element. The control element and insulating element are mounted on a first pad portion of the first lead, while the driver element on a second pad portion of the second lead. In plan view, the first pad portion has a first edge adjacent to the second pad portion in a first direction and extending in a second direction perpendicular to the first direction. The first edge has first and second ends opposite in the second direction. The second pad portion has a second edge adjacent to the first edge and extending in the second direction. The second edge has third and fourth ends opposite in the second direction. One of the third and fourth end is located between the first and second end in the second direction.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 28, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Tomohira Kikuchi