Abstract: The present invention discloses an array substrate, a manufacturing method thereof, and a display device thereof. The array substrate includes a substrate; a plurality of first thin film transistors, the first thin film transistors including a first gate electrode layer and a second gate electrode layer; a plurality of second thin film transistors, the second thin film transistors including a third gate electrode layer; and a gate electrode insulation layer disposed between the first gate electrode layer and the second gate electrode layer, and the third gate electrode layer located near a surface of a side of the substrate. The gate electrode insulation layer is silicon nitride material.

Abstract: An organic light-emitting diode (OLED) device includes a substrate, a well structure on the substrate with the well structure having a recess with side walls and a floor, a lower metal layer covering the floor and side-walls of the well, an upper conductive layer on the lower metal layer covering the floor of the well and contacting the lower metal layer, the upper conductive layer having outer edges at about an intersection of the side walls and the floor, a dielectric layer formed of an oxide of the lower metal layer covering the side walls of the well without covering the upper conductive layer, a stack of OLED layers covering at least the floor of the well, the upper conductive layer providing an electrode for the stack of OLED layers, and a light extraction layer (LEL) in the well over the stack of OLED layers and the dielectric layer.

Abstract: A semiconductor laminate film includes a silicon substrate and a semiconductor layer formed on the silicon substrate and containing silicon and germanium. The semiconductor layer having a surface roughness Rms of 1 nm or less. Further, the semiconductor layer satisfies the following relationship t?0.881×x?4.79 where t represents a thickness (nm) of the semiconductor layer, and x represents a ratio of the number of germanium atoms to a sum of the number of silicon atoms and the number of germanium atoms in the semiconductor layer. Also, the semiconductor layer being a mixed crystal semiconductor layer containing silicon and germanium.

Abstract: A display device includes a substrate, a first electrode, and a second electrode spaced from each other on the substrate, a first insulating layer on the first electrode, a first light emitting element between the first electrode and the second electrode, a second light emitting element on the first insulating layer and spaced from the first light emitting element, and a second insulating layer on the first insulating layer and covering at least a portion of the second light emitting element, wherein the first insulating layer includes at least one first opening penetrating the first insulating layer to expose a portion of the first electrode, the second insulating layer includes at least one second opening penetrating the second insulating layer to expose a portion of the first insulating layer, the at least one first opening and the at least one second opening do not overlap each other.

Abstract: A display apparatus includes a display substrate, and light emitting devices arranged on an upper surface of the display substrate. At least one of the light emitting devices includes a first LED unit including a first light emitting stack, a second LED unit including a second light emitting stack, and a third LED unit including a third light emitting stack. Each of the first to third light emitting stacks includes a first conductivity type semiconductor layer and a second conductivity type semiconductor layer. the first conductivity type semiconductor layer and the second conductivity type semiconductor layer in each of the first to third light emitting stacks are stacked in a horizontal direction with respect to the upper surface of the display substrate. At least one of the second conductivity type semiconductor layers in the first to third light emitting stacks is divided into two regions.

Abstract: A semiconductor module includes a conductive substrate, a plurality of first semiconductor elements, and a plurality of second semiconductor elements. The conductive substrate includes a first conductive portion to which the plurality of first semiconductor elements are electrically bonded, and a second conductive portion to which the plurality of second semiconductor elements are electrically bonded. The semiconductor module further includes a first input terminal, a second input terminal, and a third input terminal that are provided near the first conductive portion. The second input terminal and the third input terminal are spaced apart from each other with the first input terminal therebetween. The first input terminal is electrically connected to the first conductive portion. A polarity of the first input terminal is set to be opposite to a polarity of each of the second input terminal and the third input terminal.

Abstract: An organic light emitting display device includes: a thin film transistor disposed in a display area of a substrate; an insulating layer disposed on the thin film transistor; an organic light emitting element disposed on the insulating layer and connected to the thin film transistor; and an encapsulation layer covering the organic light emitting element. The encapsulation layer includes: a first inorganic layer extending from the organic light emitting element to a non-display area; an organic layer disposed on the first inorganic layer; a second inorganic layer extending from the organic layer to the non-display area; and an organic pattern layer disposed between the first inorganic layer and the second inorganic layer and spaced apart from the organic layer in the non-display area. At least a part of the first inorganic layer and at least a part of the second inorganic layer may contact each other in the non-display area.

Abstract: Disclosed is a manufacture method of the array substrate, including: sequentially forming a gate, a gate insulating layer, an active layer, an ohmic contact layer and a metal layer on a substrate, forming a photoetching mask on the metal layer, where thickness of the photoetching mask in a half exposure area of the mask plate is from 2000 ? to 6000 ?; etching the metal layer, the ohmic contact layer and the active layer outside a covering area of the photoetching mask; ashing the photoetching mask for a preset time with an ashing reactant, wherein the ashing reactant comprises oxygen, and the preset time is from 70 seconds to 100 seconds; and sequentially etching the metal layer, the ohmic contact layer and the active layer based on the ashed photoetching mask, and forming a channel region of the array substrate. The present disclosure further discloses an array substrate, and a display panel.

Abstract: A semiconductor module includes: a first conductive portion; a second conductive portion spaced from the first conductive portion in a first direction; first semiconductor elements electrically bonded to the first conductive portion and mutually spaced in a second direction perpendicular to the first direction; and second semiconductor elements electrically bonded to the second conductive portion and mutually spaced in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal of opposite polarity to the first input terminal; and an output terminal opposite from the two input terminals in the first direction and electrically connected to the second conductive portion.

Abstract: The present disclosure relates to an image sensor having a photodiode surrounded by a back-side deep trench isolation (BDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within an image sensing die and respectively comprises a photodiode configured to convert radiation into an electrical signal. The photodiode comprises a photodiode doping column with a first doping type surrounded by a photodiode doping layer with a second doping type that is different than the first doping type. A BDTI structure is disposed between adjacent pixel regions and extending from the back-side of the image sensor die to a position within the photodiode doping layer. The BDTI structure comprises a doped liner with the second doping type and a dielectric fill layer. The doped liner lines a sidewall surface of the dielectric fill layer.

Abstract: A pixel arrangement structure, a display method and a preparing method of a pixel arrangement structure, and a display substrate are provided. The pixel arrangement structure includes first color sub-pixel blocks, second color sub-pixel blocks, and third color sub-pixel blocks. Each of the plurality of minimum repeating regions has a rectangular shape and includes a first virtual rectangle, and the first virtual rectangle includes one first color sub-pixel block, one second color sub-pixel block and one third color sub-pixel block. Any edge of the first virtual rectangle has a non-zero included angle with a first direction, and the first direction is a row direction or a column direction. The first color sub-pixel block is on a perpendicular bisector of the first edge, the second color sub-pixel block and the third color sub-pixel block are on different sides of the perpendicular bisector of the first edge.

Abstract: A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

Abstract: A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.

Abstract: A semiconductor module includes: a first conductive portion; a second conductive portion spaced from the first conductive portion in a first direction; first semiconductor elements electrically bonded to the first conductive portion and mutually spaced in a second direction perpendicular to the first direction; and second semiconductor elements electrically bonded to the second conductive portion and mutually spaced in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal of opposite polarity to the first input terminal; and an output terminal opposite from the two input terminals in the first direction and electrically connected to the second conductive portion.

Abstract: A manufacturing method for memory includes providing a substrate; forming a first isolation layer on the substrate; forming a first mask layer on the first isolation layer; forming a second isolation layer on the first mask layer and part of the first isolation layer; forming a second mask layer on the second isolation layer; removing part of the second mask layer and part of the second isolation layer; removing the first mask layer and the remaining second mask layer; forming a third mask layer on the first isolation layer and the remaining second isolation layer; removing part of the third mask layer; and etching the remaining part of the second isolation layer and the first isolation layer below the second isolation layer, by taking the remaining third mask layer as a mask.

Abstract: A display device includes a planarization layer on a substrate, a plurality of inner banks and a plurality of outer banks arranged on the planarization layer and extending in one direction, a first alignment electrode and a second alignment electrode on the plurality of inner banks and spaced from each other, a light emitting element on the first alignment electrode and the second alignment electrode and located between the first alignment electrode and the second alignment electrode, and a first contact electrode on the first alignment electrode and contacting a first end of the light emitting element, and a second contact electrode on the second alignment electrode and contacting a second end of the light emitting element. The plurality of outer banks are in contact with the plurality of inner banks at the same layer, and are spaced from each other with the plurality of inner banks interposed therebetween.

Abstract: A light emitting device includes a substrate including first, second, third and fourth wiring portions on a top surface of a base member and arrayed in a first direction, and a connection wiring portion connecting the second and third wiring portions. The connection wiring portion includes first and second connection ends respectively connected with the second and third wiring portions, and a connection central portion connecting the first and second connection ends and having a maximum width in a second direction different from each of a maximum width of the first connection end and a maximum width of the second connection end. In the second direction, at least a part of the connection wiring portion has a width narrower than each of a maximum width of the second wiring portion and a maximum width of the third wiring portion.

Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a display panel, and an electronic apparatus. The array substrate includes: a base substrate; a light emitting layer on the base substrate; and a first electrode on a side of the light emitting layer away from the base substrate. The array substrate includes a light emitting area and a non-light emitting area, the first electrode is in the light emitting area and the non-light emitting area, and a thickness of a portion of the first electrode in the light emitting area is less than a thickness of a portion of the first electrode in the non-light emitting area.

Abstract: The present disclosure relates to an inorganic light emitting diode (LED) in which an emitting material layer (EML) includes inorganic luminescent particles dispersed in a siloxane matrix, wherein the siloxane matrix has a thickness equal to or less than a thickness of a layer of the inorganic luminescent particles, and an inorganic light emitting device including the inorganic LED. The siloxane matrix allows surface defects of the inorganic luminescent particles to be minimized and to prevent injections of holes and electrons from being delayed. The inorganic LED and the inorganic light emitting device lower their driving voltages and improve their luminous efficiency.

Abstract: A micromechanical pressure sensor device including a semiconductor base substrate of a first doping type on which an intermediate layer of the first doping type is situated, a cavity sealed by a sealing layer of a second doping type and including a reference pressure, a first grating of the second doping type, suspended inside the cavity on a buried connection region of the second doping type, the buried connection region laterally extending away from the cavity into the semiconductor base material, a second grating of the second doping type, situated on a side of the diaphragm region pointing to the cavity and suspended on the diaphragm region, the first grating and the second grating being electrically insulated from each other and forming a capacitance, a first connection electrically connected to the first grating via the buried connection region, and a second connection electrically connected to the second grating.