Patents Examined by Michelle Mandala
  • Patent number: 11837647
    Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: December 5, 2023
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Alexis Gauthier, Pascal Chevalier
  • Patent number: 11839116
    Abstract: Embodiments described herein generally relate to sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes substrate, pixel-defining layer (PDL) structures disposed over the section of the substrate, inorganic or metal overhang structures disposed on an upper surface of the PDL structures, and a plurality of sub-pixels. The PDL structures include a trench disposed in the top surface of the PDL structure. Each sub-pixel includes an anode, an OLED material disposed over and in contact with the anode, and a cathode disposed over the OLED material. The inorganic or metal overhang structures have an overhang extension that extends laterally over the trench. An encapsulation layer is disposed over the cathode and extends under at least a portion of the inorganic or metal overhang structures and along a top surface of the PDL structures.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: December 5, 2023
    Inventors: Ji-young Choung, Jungmin Lee, Chung-chia Chen, Yusin Lin, Dieter Haas, Si Kyoung Kim
  • Patent number: 11832474
    Abstract: An OLED is disclosed that includes an enhancement layer having optically active metamaterials, or hyperbolic metamaterials, which transfer radiative energy from the organic emissive material to a non-radiative mode, wherein the enhancement layer is disposed over the organic emissive layer opposite from the first electrode, and is positioned no more than a threshold distance away from the organic emissive layer, wherein the organic emissive material has a total non-radiative decay rate constant and a total radiative decay rate constant due to the presence of the enhancement layer, and the threshold distance is where the total non-radiative decay rate constant is equal to the total radiative decay rate constant; and an outcoupling layer disposed over the enhancement layer, wherein the outcoupling layer scatters radiative energy from the enhancement layer to free space.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: November 28, 2023
    Assignee: Universal Display Corporation
    Inventors: Nicholas J. Thompson, Marc A. Baldo, Michael S. Weaver, Vinod M. Menon
  • Patent number: 11830868
    Abstract: Various embodiments include methods of fabricating an array of self-aligned vertical solid state devices and integrating the devices to a system substrate. The method of fabricating a self-aligned vertical solid state device comprising: providing a semiconductor substrate, depositing a plurality of device layers on the semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers comprises an active layer and a doped conductive layer, forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer that does not substantially etch the active layer.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: November 28, 2023
    Assignee: VueReal Inc.
    Inventors: Gholamreza Chaji, Ehsanollah Fathi
  • Patent number: 11830838
    Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: November 28, 2023
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventor: Paul M. Enquist
  • Patent number: 11830856
    Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 28, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Erik Nino Tolentino, Vemmond Jeng Hung Ng, Shutesh Krishnan
  • Patent number: 11830904
    Abstract: A light sensing device includes a substrate, a gate electrode, a semiconductor layer, a dielectric layer, a first source/drain electrode, a second source/drain electrode, and a reset electrode. The gate electrode is over the substrate. The semiconductor layer is over the substrate and at least partially overlapping the gate electrode. The dielectric layer spaces the gate electrode from the semiconductor layer. The first source/drain electrode and the second source/drain electrode are respectively connected to the semiconductor layer. The semiconductor layer has a first region and a second region between the first source/drain electrode and the second source/drain electrode, the first region overlaps the gate electrode, and the second region does not overlap the gate electrode. The reset electrode is in contact with the semiconductor layer.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: November 28, 2023
    Assignee: HANNSTOUCH SOLUTION INCORPORATED
    Inventor: Sheng-Chia Lin
  • Patent number: 11825700
    Abstract: The present disclose is related to an array substrate. The array substrate may include a base substrate; a driving transistor on the base substrate; an insulating layer on the driving transistor, the insulating layer comprising a via hole above a first electrode of the driving transistor; a conductive portion on the insulating layer; and a light emitting device on the conductive portion and electrically connected to the conductive portion. The conductive portion may be electrically connected to the first electrode of the driving transistor through the via hole. The light emitting device may be above the via hole, and an orthographic projection of the light emitting device on the base substrate may cover an orthographic projection of the via hole on the base substrate.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: November 21, 2023
    Assignees: Hefel BOE Joint Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Can Yuan, Yongqian Li, Zhidong Yuan
  • Patent number: 11824053
    Abstract: An electronic device is provided. The electronic device includes a housing, a display panel, and a camera device. The housing may have an inner space. The display panel may be disposed in the inner space of the housing to be visible from an outside and may include a transmission area formed as a part of an active area thereof. The camera device may be disposed under the display panel such that the transmission area of the display panel is overlapped with an angle of view of the camera device. The transmission area contains a plurality of pixels or a plurality of wirings having an arrangement density lower than in a surrounding active area when the display panel is viewed from above. The display panel may include an opaque layer disposed thereunder, having a plurality of openings, and overlapped with the transmission area when the display panel is viewed from above.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: November 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunjea Kim, Changkeun Kim, Jaecheol Bae, Jeongyeol Lee
  • Patent number: 11817895
    Abstract: Methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, a method of manufacturing a radio-frequency device can include providing a semiconductor die including a radio-frequency circuit, a first side and a second side, and a plurality of vias, each via configured to provide an electrical connection between the first side and the second side of the semiconductor die. The method can further include mounting a filter device on the first side of the semiconductor die, the filter device in communication with the radio-frequency circuit, the radio-frequency circuit implemented in a layer on the first side of the semiconductor die and at least some of the vias coupled with the radio-frequency circuit to support an electrical connection between the radio-frequency circuit and mounting features on the second side of the semiconductor die.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: November 14, 2023
    Assignee: Skyworks Solutions, Inc.
    Inventor: James Phillip Young
  • Patent number: 11810893
    Abstract: An interposer sandwich structure includes a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes an attachment for attaching the device to the bottom interposer, and an interconnection structure connecting the top interposer to the bottom interposer. The top interposer may also be directly connected to a chip carrier in addition to the bottom interposer. The structure provides shielding and protection of the device against Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and Electromagnetic Conductivity (EMC) in miniaturized 3D packaging.
    Type: Grant
    Filed: May 31, 2021
    Date of Patent: November 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: William Emmett Bernier, Bing Dang, John Knickerbocker, Son Kim Tran, Mario J. Interrante
  • Patent number: 11807517
    Abstract: A MEMS device includes a semiconductor support body having a first cavity, a membrane including a peripheral portion, fixed to the support body, and a suspended portion. A first deformable structure is at a distance from a central part of the suspended portion of the membrane and a second deformable structure is laterally offset relative to the first deformable structure towards the peripheral portion of the membrane. A projecting region is fixed under the membrane. The second deformable structure is deformable so as to translate the central part of the suspended portion of the membrane along a first direction, and the first deformable structure is deformable so as to translate the central part of the suspended portion of the membrane along a second direction.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 7, 2023
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Dario Paci, Domenico Giusti, Irene Martini
  • Patent number: 11812608
    Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsun-Kai Tsao, Hung-Ling Shih, Po-Wei Liu, Shun-Shing Yang, Wen-Tuo Huang, Yong-Shiuan Tsair, ShihKuang Yang
  • Patent number: 11798891
    Abstract: A flexible circuitry layer may comprise a conductive mesh including a circuitry trace; and an interfacing component, comprising: a flexible substrate; a terminal electrically connected to the circuitry trace; and a connector configured to be detachably connected to an external device.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: October 24, 2023
    Assignee: LOOMIA Technologies, Inc.
    Inventors: Madison Thea Maxey, Ezgi U├žar, Janett Martinez
  • Patent number: 11793030
    Abstract: The present disclosure relates to the field of display technology, and proposes a display panel, a manufacturing method thereof, and a display device. The display panel includes an array substrate, a plurality of sub-pixels, and a plurality of divergent lenses. The array substrate includes a plurality of switch units. The plurality of sub-pixels is arranged on the array substrate, where each sub-pixel includes a plurality of light-emitting components, each light-emitting component includes a driving electrode, the driving electrode is connected to the plurality of switch units, and a gap exists between the driving electrodes of two adjacent light-emitting components. Each divergent lens is arranged on a side of a respective gap away from the array substrate. An orthographic projection of the gap on the array substrate is located in an orthographic projection of the divergent lens on the array substrate.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: October 17, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Sheng Xu, Shipei Li
  • Patent number: 11791181
    Abstract: Systems and methods for thermal treatment of a workpiece are provided. In one example, a method for conducting a treatment process on a workpiece, such as a thermal treatment process, an annealing treatment process, an oxidizing treatment process, or a reducing treatment process in a processing apparatus is provided. The processing apparatus includes a plasma chamber and a processing chamber. The plasma chamber and the processing chamber are separated by a plurality of separation grids or grid plates. The separation grids or grid plates operable to filter ions generated in the plasma chamber. The processing chamber has a workpiece support operable to support a workpiece.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: October 17, 2023
    Assignees: BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY CO., LTD, MATTSON TECHNOLOGY, INC.
    Inventors: Ting Xie, Hua Chung, Haochen Li, Xinliang Lu, Shawming Ma, Haichun Yang, Michael X. Yang
  • Patent number: 11793035
    Abstract: The present disclosure provides a display panel, a display device including the display panel and a method of manufacturing the display panel. The display panel includes a substrate; a pixel-defining layer disposed on the substrate, wherein the pixel-defining layer defines a plurality of sub-pixel regions arranged in rows and columns; and an organic light emitting element disposed in at least one of the plurality of sub-pixel regions, wherein a side of the pixel-defining layer away from the substrate is provided with a groove, the groove has a depth less than a thickness of the pixel-defining layer and the groove is disposed between the organic light emitting elements that are adjacent to each other and emit light of different colors.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: October 17, 2023
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xianghua Nan, Qingyun Bai
  • Patent number: 11785831
    Abstract: An opto-electronic device includes: a first electrode; an organic layer disposed over the first electrode; a nucleation promoting coating disposed over the organic layer; a nucleation inhibiting coating covering a first region of the opto-electronic device; and a conductive coating covering a second region of the opto-electronic device.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: October 10, 2023
    Assignee: OTI Lumionics Inc.
    Inventors: Yi-Lu Chang, Qi Wang, Michael Helander, Jacky Qiu, Zhibin Wang, Thomas Lever
  • Patent number: 11777015
    Abstract: Microfabrication of a collection of transistor types on multiple transistor planes in which both HV (high voltage transistors) and LV (low-voltage transistors) stacks are designed on a single substrate. As high voltage transistors require higher drain-source voltages (Vds), higher gate voltages (Vg), and thus higher Vt (threshold voltage), and relatively thicker 3D gate oxide thicknesses, circuits made as described herein provide multiple different threshold voltages devices for both low voltage and high voltage devices for NMOS and PMOS, with multiple different gate oxide thickness values to enable multiple transistor planes for 3D devices.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: October 3, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 11776929
    Abstract: A semiconductor device includes: an inner substrate on which a semiconductor chip is mounted, and has a surface on which terminals including electric path terminals are formed; a lead frame which has a chip connecting electrode portion which is electrically connected to a surface of the semiconductor chip via a conductive bonding member, substrate connecting electrode portions which are electrically connected to the electric path terminals of the inner substrate, and horizontal surface support portions which bulge to the outside from the chip connecting electrode portion or the substrate connecting electrode portions; and pin terminals which are mounted upright over the inner substrate in a direction perpendicular to flat surfaces of the substrate connecting electrode portions of the lead frame, wherein the horizontal surface support portions bulge to the outside of the inner substrate.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 3, 2023
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Soichiro Umeda, Atsushi Kyutoku