Abstract: A display panel and a display device are disclosed. The display panel includes a substrate, a cathode suppression layer, a cathode, and a polarizer. The cathode suppression layer includes a first cathode suppression portion located in a first light-transmitting area. The cathode is located in a first light-emitting area and the first light-transmitting area, and covers at least part of the first cathode suppression portion. The polarizer includes a first light-transmitting portion located in the first light-transmitting area. A projection of the first light-transmitting portion projected on the substrate is located within a boundary of a projection of the first cathode suppression portion projected on the substrate.

Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

Abstract: Provided are an apparatus for manufacturing a display device and a method of manufacturing the display device. The apparatus for manufacturing a display device includes a droplet discharge unit including a nozzle that discharges a droplet, at least one sensor that senses a partial shape of an outer surface of the droplet projected onto a plane and a cross-sectional shape of the droplet discharge unit projected onto the plane, the plane being on a falling path of the droplet discharged from the droplet discharge unit, and a controller that calculates, based on a result sensed by the at least one sensor, at least one of a volume of the droplet, a falling speed of the droplet, a discharge angle at which the droplet is discharged from the nozzle, and a falling path of the droplet moving from the nozzle to a substrate.

Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a substrate, the substrate comprising a blind hole area; a buffer layer covering one side of the substrate; an organic film layer provided on the surface of the buffer layer away from the substrate and having a first opening in the blind hole area; a passivation layer provided on the side of the organic film layer away from the substrate and having a second opening in the blind hole area; and a transparent electrode layer covering the passivation layer and the buffer layer in the second opening.

Abstract: An opto-electronic device includes: a first electrode; an organic layer disposed over the first electrode; a nucleation promoting coating disposed over the organic layer; a nucleation inhibiting coating covering a first region of the opto-electronic device; and a conductive coating covering a second region of the opto-electronic device.

Abstract: The present disclosure relates to a CMUT transducer (200) comprising: —a conductive or semiconductor substrate (201) coated with a stack of one or a plurality of dielectric layers (203, 213); —a cavity (205, 215) formed in said stack; —a conductive or semiconductor membrane (221) suspended above the cavity; —at the bottom of the cavity, a conductive region (209) in contact with the upper surface of the substrate, said conductive region being interrupted on a portion of the upper surface of the substrate; and—in the cavity, a stop structure (207) made of a dielectric material localized on or above the area of interruption of the conductive region (209).

Abstract: An object of the present disclosure is to facilitate thermal design in a semiconductor device in which MOSFETs and SBDs are connected in antiparallel. The semiconductor device includes a MOSFET chip provided on a first pattern, whose drain electrode and source electrode are electrically connected to the first pattern and a second pattern, respectively, an SBD chip provided on a third pattern, whose cathode electrode and anode electrode are electrically connected to the third pattern and fourth pattern, respectively, a drain main terminal connected to the first pattern, a source main terminal connected to the second pattern, a cathode main terminal connected to the third pattern, and an anode main terminal connected to the fourth pattern. At least one of between the drain main terminal and the cathode main terminal and between the source main terminal and the anode main terminal is not electrically connected.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode, and a third nitride-based semiconductor layer. The first nitride-based semiconductor layer has at least one trench. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and spaced apart from the trench. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate electrode is disposed above the second nitride-based semiconductor layer and between the source and drain electrodes, so as to at least define a drift region between the gate electrode and the drain electrode and overlaps with the trench. The third nitride-based semiconductor layer is at least disposed in the trench and extends upward from the trench to make contact with the second nitride-based semiconductor layer.

Abstract: A display device includes: a light-emitting diode including a first electrode, a second electrode arranged on the first electrode, and an intermediate layer between the first electrode and the second electrode; a bus electrode spaced apart from the first electrode of the light-emitting diode; a bank layer covering an edge of the first electrode and an edge of the bus electrode, and exposing a portion of the first electrode and a portion of the bus electrode; and an insulating pattern layer arranged on the bus electrode, and including a first opening overlapping a first opening, wherein the second electrode contacts the bus electrode through the first opening of the insulating pattern layer.

Abstract: A microelectronic device comprises array regions individually comprising memory cells comprising access devices and storage node device, digit lines coupled to the access devices and extending in a first direction, word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction. The capacitor regions individually comprise additional control logic devices vertically overlying the memory cells, and capacitor structures within horizontal boundaries of the additional control logic devices. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (GAA) structure surrounding the nanostructured channel region. The GAA structure includes a high-K (HK) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pWFM) layer disposed on the HK gate dielectric layer, a bimetallic nitride layer interposed between the HK gate dielectric layer and the pWFM layer, an n-type work function metal (nWFM) layer disposed on the pWFM layer, and a gate metal fill layer disposed on the nWFM layer. The pWFM layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.

Abstract: A power semiconductor apparatus provided with a first conductor section connected to a direct-current terminal for transmitting direct-current power; a second conductor section connected to an alternating-current terminal for transmitting alternating-current power; a semiconductor element which is disposed between the first conductor section and the second conductor section and is for converting the direct-current power to the alternating-current power; and an interposition section disposed between the first conductor section and the second conductor section, in which the interposition section has a first conductor layer connected to the first conductor section, a second conductor layer connected to the second conductor section, and a plurality of insulation layers disposed between the first conductor layer and the second conductor layer, with one or a plurality of third conductor layers sandwiched between the plurality of insulation layers.

Abstract: A pixel defining structure includes a first sub-pixel defining structure surrounding a first sub-pixel region configured to form a first sub-pixel having a first color. The first sub-pixel defining structure includes a lyophilic portion one the bottom side of the first sub-pixel region and a lyophobic portion on a side opposite to the bottom side. The pixel defining structure includes a second sub-pixel defining structure surrounding a second sub-pixel region configured to form a second sub-pixel having a second color. The second sub-pixel defining structure includes a lyophilic portion one the bottom side of the second sub-pixel region and a lyophobic portion on a side opposite to the bottom side. The second color is different from the first color. Thicknesses of the lyophilic portion of the first sub-pixel defining structure and the lyophilic portion of the second sub-pixel defining structure are different.

Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

Abstract: Provided are a chip and a memory, relating to the technical field of semiconductors, and intended to solve the technical problem of low qualification rate of chips. The chip includes a base in which a through hole penetrating through the base is provided. A conductive column is provided in the through hole. A first surface of the base is provided with a first annular groove which surrounds the conductive column. A first isolator is provided in the first annular groove, and a first air gap extending along a circumferential direction of the first annular groove is formed in the first isolator.

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate, the substrate having a plurality of discrete bit lines, and a capacitor contact hole being provided between adjacent bit lines; forming a fill film, the fill film being provided with a gap region; etching the fill film by using a first etch process to open the gap region, the remaining fill film acting as a first fill layer; sequentially stacking at least two base fill layers on a surface of the first fill layer, the base fill layer farthest from the substrate filling the remaining capacitor contact hole; decreasing a doping concentration of the base fill layer, layer by layer and etching the first fill layer and at least part of the base fill layers by using a second etch.

Abstract: Provided is a display panel, including: a base substrate, a light emitting device layer provided on the base substrate and including light emitting devices, and a light adjustment structure layer provided at a side of the light emitting device layer facing away from the base substrate and including light adjustment units and a dielectric layer covering the light adjustment units. Each light adjustment unit has a smaller refractive index than the dielectric layer and includes a light adjustment sub-section and a through hole penetrating the light adjustment unit in a direction perpendicular to the base substrate. The through hole overlaps one light emitting device, and the light adjustment sub-section surrounds the through hole. For one light adjustment unit, a thickness of the light adjustment sub-section gradually increases in a direction from the through hole to the light adjustment sub-section.

Abstract: Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.