Abstract: The present disclosure provides an array substrate and a manufacturing method thereof, a display panel, and an electronic apparatus. The array substrate includes: a base substrate; a light emitting layer on the base substrate; and a first electrode on a side of the light emitting layer away from the base substrate. The array substrate includes a light emitting area and a non-light emitting area, the first electrode is in the light emitting area and the non-light emitting area, and a thickness of a portion of the first electrode in the light emitting area is less than a thickness of a portion of the first electrode in the non-light emitting area.

Abstract: A light-emitting module including a substrate, a light-emitting device disposed on the substrate, a lens, and an optical sensor. The light-emitting device includes at least one light-emitting element and a light-transmissive member disposed on a light extraction surface of the at least one light-emitting element. The lens is disposed apart from the light-emitting device at a position where the lens faces the light-emitting device. The optical sensor has an upper surface including a light-receiving surface to receive light through the lens and is disposed on the substrate at a position where at least a part of the light-receiving surface faces the lens. A center of the light-emitting device is located at a center of the lens in a plan view.

Abstract: A micromechanical pressure sensor device including a semiconductor base substrate of a first doping type on which an intermediate layer of the first doping type is situated, a cavity sealed by a sealing layer of a second doping type and including a reference pressure, a first grating of the second doping type, suspended inside the cavity on a buried connection region of the second doping type, the buried connection region laterally extending away from the cavity into the semiconductor base material, a second grating of the second doping type, situated on a side of the diaphragm region pointing to the cavity and suspended on the diaphragm region, the first grating and the second grating being electrically insulated from each other and forming a capacitance, a first connection electrically connected to the first grating via the buried connection region, and a second connection electrically connected to the second grating.

Abstract: Various embodiments include methods and apparatus having a number of charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric region, the blocking dielectric region located on a charge trap region of the charge trap structure. At least a portion of the gate can be separated by a void from a region which the charge trap structure is directly disposed. Additional apparatus, systems, and methods are disclosed.

Abstract: A semiconductor device including a static random access memory (SRAM) device includes a first SRAM array including a first plurality of bit cells arranged in a matrix; a second SRAM array including a second plurality of bit cells arranged in a matrix; and a plurality of abutting dummy cells disposed between the first SRAM array and the second SRAM array. Each of the plurality of abutting dummy cells includes a plurality of dummy gate electrode layers and a plurality of dummy contacts. The semiconductor device further includes a first-type well continuously extending from the first SRAM array to the second SRAM array. The first-type well is in direct contact with portions of the plurality of dummy contacts.

Abstract: According to an aspect, a display apparatus includes: a substrate; a plurality of pixels arrayed on the substrate; a plurality of inorganic light-emitting elements that are provided in the pixels, respectively; a transistor provided to a first surface of the substrate and coupled to one of the inorganic light-emitting elements; wiring provided to the first surface of the substrate and coupled to the transistor; and a circular polarization plate provided on a first side of the substrate.

Abstract: An object is to suppress a lift of an external terminal when an external force is applied, thereby improving the reliability of a semiconductor device. A heat radiating plate 10 having on one main surface a circuit area 54 in which a semiconductor element 50 is arranged, a pair of terminals 31 and 32 connected to the semiconductor element 50, a resin housing 20 that covers the circuit area 54 of the heat radiating plate 10 to seal the semiconductor element 50, and has a terminal surface 22 formed on an upper surface, a pair of side surfaces in the longitudinal direction, and a pair of front and rear surfaces in the lateral direction, are included. The resin housing 20 has a pair of bending contact portions 22e and 23e that come into respectively contact with the pair of terminals 31 and 32 to define bending positions of the terminals 31 and 32. The pair of bending contact portions 22e and 23e are formed to have different heights.

Abstract: Device, package structure and method of forming the same are disclosed. The device includes a die encapsulated by an encapsulant, a conductive structure aside the die, and a dielectric layer overlying the conductive structure. The conductive structure includes a through via in the encapsulant, a redistribution line layer overlying the through via, and a seed layer overlying the redistribution line layer. The dielectric layer includes an opening, wherein the opening exposes a surface of the conductive structure, the opening has a scallop sidewall, and an included angle between a bottom surface of the dielectric layer and a sidewall of the opening is larger than about 60 degrees.

Abstract: A display panel is provided. A pixel defining layer of the display panel includes a first defining layer and a second defining layer, wherein the first defining layer includes a first base body and first magnets dispersed in the first base body, and the second defining layer includes a second base body and second magnets dispersed in the second base body; both the first base body and the second base body are hydrophobic and elastic; and a side face of the first base body perpendicular to a bearing surface of the substrate and a side face of the second base body perpendicular to the bearing surface of the substrate being in contact with each other.

Abstract: A synthetic antiferromagnetic structure for a spintronic device is disclosed and has an FL2/Co or Co alloy/antiferromagnetic coupling/Co or Co alloy/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. Antiferromagnetic coupling is improved by inserting a Co or Co alloy dusting layer on top and bottom surfaces of the antiferromagnetic coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)n laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the synthetic antiferromagnetic structure.

Abstract: An electro-optical device comprising a plurality of pixels. Each of the plurality of pixels includes a first sub pixel and a second sub pixel that are arrayed in the first direction, a third sub pixel and a fourth sub pixel that are arrayed in the first direction, and a color filter corresponding to each of the first sub pixel, the second sub pixel, the third sub pixel, and the fourth sub pixel. Each of the first sub pixel, the second sub pixel, the third sub pixel, and the fourth sub pixel including a light-emitting element includes a light-emitting region, a supply circuit for supplying current to the light-emitting element, and a contact region in which a contact for electrically connecting the light-emitting element to the supply circuit is disposed.

Abstract: An electrical apparatus includes a semiconductor element, conductors and a covering resin. The conductors are connected to the semiconductor element. At least one of the conductors extends in a first direction. The covering resin covers the semiconductor element and a portion of each of the conductors. The conductors respectively include covering portions and exposing portions. Each of the covering portions is covered by the covering resin. Each of the exposing portions is exposed from the covering resin. The conductors are aligned in a second direction. Two of the exposing portions closest to each other are spaced apart in each of the second direction and a third direction. The third direction is perpendicular to the first direction and the second direction. A shortest separation distance between two closest covering portions is shorter than a shortest separation distance between two closest exposing portions.

Abstract: A detection module for a display device includes: a substrate; a detector disposed on the substrate to detect an external signal; a sensor driving circuit disposed on the substrate to drive the detector; and a light shielding layer to block an external light from entering the sensor driving circuit and to receive a light blocking voltage.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip having a first electrode on a first surface, a metal plate, and a first conductive bonding sheet that is disposed between the first surface of the semiconductor chip and the metal plate and bonds the first electrode to the metal plate.

Abstract: A display device includes a pixel electrode including silver, a pixel-defining film on the pixel electrode and exposing the pixel electrode, a barrier layer on the pixel electrode and the pixel-defining film and including a low-resistance area and a high-resistance area which has a higher resistance than the low-resistance area, an emission layer on the barrier layer, and a common electrode on the emission layer. The low-resistance area of the barrier layer overlaps with the pixel electrode, and the high-resistance area of the barrier layer overlaps with the pixel-defining film.

Abstract: A pixel arrangement structure, a display method and a preparing method of a pixel arrangement structure, and a display substrate are provided. The pixel arrangement structure includes first color sub-pixel blocks, second color sub-pixel blocks, and third color sub-pixel blocks. Each of the plurality of minimum repeating regions has a rectangular shape and includes a first virtual rectangle, and the first virtual rectangle includes one first color sub-pixel block, one second color sub-pixel block and one third color sub-pixel block. Any edge of the first virtual rectangle has a non-zero included angle with a first direction, and the first direction is a row direction or a column direction. The first color sub-pixel block is on a perpendicular bisector of the first edge, the second color sub-pixel block and the third color sub-pixel block are on different sides of the perpendicular bisector of the first edge.

Abstract: A nonvolatile memory device includes a substrate including a cell region and a peripheral circuit region, a stacked structure on the cell region, the stacked structure including a plurality of gate patterns separated from each other and stacked sequentially, a semiconductor pattern connected to the substrate through the stacked structure, a peripheral circuit element on the peripheral circuit region, a first interlayer insulating film on the cell region and the peripheral circuit region, the first interlayer insulating film covering the peripheral circuit element, and a lower contact connected to the peripheral circuit element through the first interlayer insulating film, a height of a top surface of the lower contact being lower than or equal to a height of a bottom surface of a lowermost gate pattern of the plurality of gate patterns on the first interlayer insulating film.

Abstract: An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk, the display may include active and/or passive leakage-mitigating structures. The passive leakage-mitigating structures may have an undercut that causes discontinuities in the overlying OLED layers. Active leakage-mitigating structures may include a conductive layer (e.g., a conductive ring) that drains leakage current to ground. Alternatively, the active leakage-mitigating structures may include a gate electrode modulator with a variable voltage that stops the current flow laterally.

Abstract: According to one embodiment, a display device includes a base, a driving transistor placed on the base, a first insulating layer placed on the driving transistor, a cathode electrode placed on the first insulating layer, an organic layer including a light-emitting layer placed on the cathode electrode, an anode electrode that covers the organic layer, a second insulating layer placed on the first insulating layer and having an opening superposed on the cathode electrode, and a barrier wall placed on the second insulating layer. The anode electrode is electrically connected to the driving transistor through a first contact hole formed in the first insulating layer and the second insulating layer.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding layer having a plurality of first bonding contacts, and a first via structure extending vertically through the first bonding layer and into the first semiconductor structure. The second semiconductor structure includes a second bonding layer having a plurality of second bonding contacts, and a second via structure extending vertically through the second bonding layer and into the second semiconductor structure. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, the first via structure is in contact with the second via structure, and sidewalls of the first via structure and the second via structures have a staggered profile at the bonding interface.