Patents Examined by Minh-Loan T Tran
  • Patent number: 9081122
    Abstract: A light blocking member including a metal particle and a ceramic material and a display device including the same.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: July 14, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Eok Shin, Dae-Woo Lee, Won-Pil Lee, Ho-Jin Yoon, Yong-Woo Park, Kyung-Min Choi
  • Patent number: 9029939
    Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Jong-Wook Lee, Jong-Hyuk Kang
  • Patent number: 8912622
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor substrate, a first first-conductivity-type semiconductor layer, a second first-conductivity-type semiconductor layer, a second-conductivity-type bottom layer, a Schottky metal, and a cathode electrode. The first first-conductivity-type semiconductor layer is provided on the semiconductor substrate and has a lower first-conductivity-type impurity concentration than the semiconductor substrate. The second first-conductivity-type semiconductor layer is provided on the first first-conductivity-type semiconductor layer and has a higher first-conductivity-type impurity concentration than the first first-conductivity-type semiconductor layer. The Schottky metal is provided on the second first-conductivity-type semiconductor layer. The Schottky metal contacts with partly the first first-conductivity-type semiconductor layer.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Arai, Takashi Tabuchi
  • Patent number: 8901590
    Abstract: Phototherapy devices for phototherapy treatment of a patient include a light emitter for emitting light received from a light source. Means may be provided for altering the amount of power to the light source in response to a change in light output to maintain a substantially constant light output. The light source may comprise one or more LEDs that generate a blue light output and at least one other LED that generates a different color light output.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 2, 2014
    Assignee: Lumitex, Inc.
    Inventor: Jeffrey B. Williams
  • Patent number: 8896075
    Abstract: A compound semiconductor radiation detector includes a body of compound semiconducting material having an electrode on at least one surface thereof. The electrode includes a layer of a compound of a first element and a second element. The first element is platinum and the second element includes at least one of the following: chromium, cobalt, gallium, germanium, indium, molybdenum, nickel, palladium, ruthenium, silicon, silver, tantalum, titanium, tungsten, vanadium, zirconium, manganese, iron, magnesium, copper, tin, or gold. The layer can further include sublayers, each of which is made from a different one of the second elements and platinum as the first element.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: November 25, 2014
    Assignee: eV Products, Inc.
    Inventors: Gary L. Smith, Csaba Szeles
  • Patent number: 8895991
    Abstract: An organic electroluminescent display and method of manufacturing the same are disclosed. In one aspect, the organic electroluminescent display includes a substrate and a first electrode disposed on the substrate. It also includes a pixel definition layer disposed on the first electrode, wherein the pixel definition layer has an opening portion formed in an area overlapped with the first electrode. It further includes a lyophilic layer disposed on the first electrode and the pixel definition layer, an organic light emitting layer disposed on the lyophilic layer, and a second electrode disposed on the organic light emitting layer. The lyophilic layer includes a center portion and an edge portion. The center portion is disposed on the first electrode through the opening portion and includes at least one recess portion formed therein. The edge portion is extended from the center portion and disposed on the pixel definition layer.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: A Rong Lee, Young-il Kim, Euigyu Kim
  • Patent number: 8884405
    Abstract: An integrated circuit includes a substrate and passivation layers. The passivation layers include a bottom dielectric layer formed over the substrate for passivation, a doped dielectric layer formed over the bottom dielectric layer for passivation, and a top dielectric layer formed over the doped dielectric layer for passivation.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chi Chuang, Kun-Ming Huang, Hsuan-Hui Hung, Ming-Yi Lin
  • Patent number: 8884342
    Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
  • Patent number: 8884262
    Abstract: A non-volatile memory device is provided wherein a lower molding layer is formed on a substrate; a first horizontal interconnection is formed on the lower molding layer; an upper molding layer is formed on the first horizontal interconnection; a pillar is formed connected to the substrate by vertically passing through the upper molding layer, the first horizontal interconnection and the lower molding layer. The pillar has a lower part and an upper part, wherein the lower part is disposed on the same level as the first horizontal interconnection and has a first width and the upper part is disposed on a higher level than the first horizontal interconnection and has a second width different from the first width.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Su Ju, Sun-Jung Kim, Soo-Doo Chae
  • Patent number: 8878210
    Abstract: A light emitting device comprising: a substrate, wherein the substrate comprises a first major surface, a second major surface opposite to the first major surface, and a sidewall wherein the entire sidewall is a substantially textured surface with a depth of 10˜150 ?m; and a light emitting stack layer formed on the substrate.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: November 4, 2014
    Assignee: Epistar Corporation
    Inventor: Tzu-Chieh Hsu
  • Patent number: 8872263
    Abstract: The semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: October 28, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yuki Nakano, Ryota Nakamura
  • Patent number: 8872294
    Abstract: Photonic structures and methods of formation are disclosed in which a photo detector interface having crystalline misfit dislocations is displaced with respect to a waveguide core to reduce effects of dark current on a detected optical signal.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Zvi Sternberg, Ofer Tehar-Zahav
  • Patent number: 8872183
    Abstract: Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Chang, Changhyun Lee, Byoungkeun Son, Jin-Soo Lim
  • Patent number: 8872210
    Abstract: According to one embodiment, a semiconductor light emitting device includes a light emitting element, a phosphor layer, and a fluorescent reflection film. The phosphor layer has a transparent medium, a phosphor dispersed in the transparent medium, and a particle dispersed in the transparent medium. The phosphor is excited by the excitation light so as to emit a fluorescence. The particle is a magnitude of not more than 1/10 a wavelength of the excitation light. The particle has a different refractive index from a refractive index of the transparent medium. The fluorescent reflection film is provided between the light emitting element and the phosphor layer. The fluorescent reflection film has a higher reflectance with respect to a fluorescent wavelength of the phosphor, than a reflectance with respect to the wavelength of the excitation light.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Furuyama, Yosuke Akimoto, Miyoko Shimada, Akihiro Kojima, Yoshiaki Sugizaki
  • Patent number: 8866143
    Abstract: The invention primarily provides gate electrodes and gate wirings permitting large-sized screens for active matrix-type display devices, wherein, in order to achieve this object, the construction of the invention is a semiconductor device having, on the same substrate, a pixel TFT provided in a display region and a driver circuit TFT provided around the display region, wherein the gate electrodes of the pixel TFT and the driver circuit TFT are formed from a first conductive layer, the gate electrodes are in electrical contact through connectors with gate wirings formed from a second conductive layer, and the connectors are provided outside the channel-forming regions of the pixel TFT and the driver circuit TFT.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Toru Takayama, Toshiji Hamatani
  • Patent number: 8860194
    Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 14, 2014
    Assignee: International Rectifier Corporation
    Inventors: Ling Ma, Andrew N. Sawle, David Paul Jones, Timothy D. Henson, Niraj Ranjan, Vijay Viswanathan, Omar Hassen
  • Patent number: 8860069
    Abstract: A light-emitting device package. The light-emitting device package includes a lead frame comprising a plurality of separate leads; a molding member that fixes the plurality of leads and comprises an opening portion that exposes the lead frame; and a light-emitting device chip that is attached on the lead frame in the opening portion and emits light through an upper surface portion of the light-emitting device chip, wherein a height of the molding member is lower than a height of the light-emitting device chip with respect to the lead frame.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheol-jun Yoo, Young-hee Song
  • Patent number: 8853707
    Abstract: Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Dae Keun Park
  • Patent number: 8853706
    Abstract: Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package with a stamped leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked atop a source of the III-nitride transistor, and a stamped leadframe comprising a first bent lead coupled to a gate of the III-nitride transistor and the anode of the diode, and a second bent lead coupled to a drain of the III-nitride transistor. The bent leads expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Dae Keun Park
  • Patent number: 8853690
    Abstract: An object is to provide a transistor including an oxide layer which includes Zn and does not include a rare metal such as In or Ga. Another object is to reduce an off current and stabilize electric characteristics in the transistor including an oxide layer which includes Zn. A transistor including an oxide layer including Zn is formed by stacking an oxide semiconductor layer including insulating oxide over an oxide layer so that the oxide layer is in contact with a source electrode layer or a drain electrode layer with the oxide semiconductor layer including insulating oxide interposed therebetween, whereby variation in the threshold voltage of the transistor can be reduced and electric characteristics can be stabilized.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: October 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Hideyuki Kishida