Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.

Abstract: In a semiconductor device comprising sophisticated high-k metal gate structures formed in accordance with a replacement gate approach, semiconductor-based resistors may be formed above isolation structures substantially without being influenced by the replacement gate approach. Consequently, enhanced area efficiency may be achieved compared to conventional strategies, in which the resistive structures may have to be provided on the basis of a gate electrode metal, while, nevertheless, a low parasitic capacitance may be accomplished due to providing the resistive structures above the isolation structure.

Abstract: A reproducing apparatus includes: a digital signal processing block configured to execute first boost processing for setting a volume level for an entered digital audio signal and boosting an amplitude level of the signal; a digital-to-analog conversion block configured to convert the digital audio signal into an analog one; an analog signal processing block configured to execute second boost processing for boosting an amplitude level of the analog audio signal; an analog volume adjusting block configured to set a volume level for the analog audio signal from the analog signal processing block; a loudspeaker configured to output the analog audio signal from the analog volume adjusting block; an operating block configured to indicate a volume level of an audio signal from the loudspeaker and turn on/off the boost processing for the audio signals; and a control block configured to control components in accordance with an operation by the operating block.

Abstract: Methods and systems for packaging MEMS devices such as interferometric modulator arrays are disclosed. One embodiment of a MEMS device package structure includes a seal with a chemically reactant getter. Another embodiment of a MEMS device package comprises a primary seal with a getter, and a secondary seal proximate an outer periphery of the primary seal. Yet another embodiment of a MEMS device package comprises a getter positioned inside the MEMS device package and proximate an inner periphery of the package seal.

Abstract: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged on a semiconductor substrate, in which each of the pixels includes a photoelectric converting portion and a charge converting portion for converting a charge generated by photoelectric conversion into a pixel signal and blooming is suppressed by controlling a substrate voltage of the semiconductor substrate.

Abstract: According to one embodiment, a semiconductor light-emitting device includes a first semiconductor layer, a second semiconductor layer, a light-emitting layer, a third semiconductor layer and a first electrode. The first semiconductor layer of a first conductivity type has a first major surface provided with a first surface asperity. The second semiconductor layer of a second conductivity type is provided on an opposite side of the first semiconductor layer from the first major surface. The light-emitting layer is provided between the first and second semiconductor layers. The first semiconductor layer is disposed between a third semiconductor layer and the light-emitting layer. The third semiconductor layer has an impurity concentration lower than an impurity concentration of the first semiconductor layer, and includes an opening exposing the first surface asperity.

Abstract: Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed.

Abstract: A thin-film transistor includes: an organic semiconductor layer; and a source electrode and a drain electrode spaced apart from each other and disposed to respectively overlap the organic semiconductor layer. The organic semiconductor layer INCLUDES: a lower organic semiconductor layer; and an upper organic semiconductor layer formed on the lower organic semiconductor layer and having solubility and conductivity higher than the lower organic semiconductor layer. The lower organic semiconductor layer extends from an area overlapping the source electrode to an area overlapping the drain electrode, while the upper organic semiconductor layer is disposed in each of the area overlapping the source electrode and the area overlapping the drain electrode so that the respective upper organic semiconductor layers are spaced apart from each other.

Abstract: An LED lighting device comprises a plurality of light emitting units which is configured to emit visible light having different colors which are mixed with each other to produce a white light. Each the light emitting units is composed of an LED chip and a phosphor. The LED chip is configured to generate light. The phosphor has a property of giving off a light of a predetermined color when the phosphor is excited by the light from the LED chip. The LED chip is selected from a group consisting of a blue LED chip, a UV LED chip, ad a violet LED chip. Each the phosphor is selected to give off the light of a predetermined color different from one another.

Abstract: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.

Abstract: Non-planar transistors, such as FinFETs, may be formed in a bulk configuration in the context of a replacement gate approach, wherein the semiconductor fins are formed during the replacement gate sequence. To this end, in some illustrative embodiments, a buried etch mask may be formed in an early manufacturing stage on the basis of superior process conditions.

Abstract: A light emitting device includes a substrate having a rectangular outer shape in a top view, a plurality of LED chips, a resin frame formed on the primary surface of the substrate and provided annularly so as to surround a mounting area in which the LED chips are provided, an anode-side electrode land and a cathode-side electrode land which are electrodes to be connected to an external voltage supply of said light emitting device. An electrode wiring pattern may be formed on the primary surface of the substrate including (i) an anode line extending from the anode-side electrode land to a portion under the resin frame and (ii) a cathode line extending from the cathode-side electrode land to the other portion under the resin frame.

Abstract: A transistor advantageously embodied in a laterally diffused metal oxide semiconductor device having a gate located over a channel region recessed into a semiconductor substrate and a method of forming the same. In one embodiment, the laterally diffused metal oxide semiconductor device includes a source/drain having a lightly doped region located adjacent the channel region and a heavily doped region located adjacent the lightly doped region. The laterally diffused metal oxide semiconductor device further includes an oppositely doped well located under and within the channel region, and a doped region, located between the heavily doped region and the oppositely doped well, having a doping concentration profile less than a doping concentration profile of the heavily doped region.

Abstract: In a semiconductor device, an IGBT cell includes a trench passing through a base layer of a semiconductor substrate to a drift layer of the semiconductor substrate, a gate insulating film on an inner surface of the trench, a gate electrode on the gate insulating film, a first conductivity-type emitter region in a surface portion of the base layer, and a second conductivity-type first contact region in the surface portion of the base layer. The IGBT cell further includes a first conductivity-type floating layer disposed within the base layer to separate the base layer into a first portion including the emitter region and the first contact region and a second portion adjacent to the drift layer, and an interlayer insulating film disposed to cover an end of the gate electrode. A diode cell includes a second conductivity-type second contact region in the surface portion of the base layer.

Abstract: The present application provides an optoelectronic semiconductor device, comprising: a substrate; an optoelectronic system on the substrate; a barrier layer on the optoelectronic system, wherein the barrier layer thickness is not smaller than 10 angstroms; and an electrode on the barrier layer.

Abstract: An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation.

Abstract: This invention relates to the mechanical protection using digital processing and a predictive estimation of instantaneous displacement of the voice coil in a loudspeaker transducer. The invention solves the problem of limiting the coil displacement of the transducer by applying a look-a-head based linear or non-linear predictor and a controller operating directly on the displacement signal in order to finally convert back into the incoming signal domain.

Abstract: A semiconductor light-receiving device includes two lenses; and a concave region, a height of the sidewall being higher than a top of the lenses, a distance between a position H and a lower edge of the sidewall vertical to a line segment C1 being grater than following condition: {(r+L)2?(W/2)2}1/2 where: C1 is a line segment connecting centers of the lenses; H is a midpoint of the C1; r is a radius of the lenses; W is an interval between the centers; and C2 is a lines passing through the centers in a direction vertical to the C1, wherein: the lower edge of the concave portion in an outer side of a region between the C2 is concentrically formed so as to have a distance of (r+L) from the center of the lenses; and W is following condition: W<2 (r+L).

Abstract: A light-emitting device package and a method of manufacturing the light-emitting device package. The light-emitting device package includes a wiring substrate; a Zener diode mounted on a first region of the wiring substrate; a light-emitting device chip mounted on the first region and a second region of the wiring substrate; and a molding member for fixing at least a portion of the wiring substrate, wherein the Zener diode is embedded in the molding member.

Abstract: Provided is a metal foil laminate that: has heat resistance; has high reflectance in the visible light range; has little decrease in reflectance in environments with a high-temperature thermal load; is compatible with large surface areas; and can be used for printed circuit boards for mounting LEDs that have excellent adhesion with metals. The metal foil laminate is characterized in that: a laminate has metal foil on at least one side of a resin layer (A) containing a polyorganosiloxane and an inorganic filler; the 90° peel strength between said resin layer (A) and said metal foil is at least 0.95 kN/m, and the mean reflectance at wavelengths of 400 to 800 nm on the surface that is exposed when the resin layer (A) is exposed by peeling and removing said metal foil is at least 80%; and the decrease in the reflectance at a wavelength of 470 nm after being treated with heat for 10 minutes at 260° C. is not more than 5%.