Patents Examined by Minh-Loan T Tran
  • Patent number: 8803139
    Abstract: A method is provided for fabricating a printed organic thin film transistor (OTFT) with a patterned organic semiconductor using a fluropolymer banked crystallization well. In the case of a bottom gate OTFT, a substrate is provided and a gate electrode is formed overlying the substrate. A gate dielectric is formed overlying the gate electrode, and source (S) and drain (D) electrodes are formed overlying the gate dielectric. A gate dielectric OTFT channel interface region is formed between the S/D electrodes. A well with fluropolymer containment and crystallization banks is then formed, to define an organic semiconductor print area. The well is filled with an organic semiconductor, covering the S/D electrodes and the gate dielectric OTFT channel interface. Then, the organic semiconductor is crystallized. Predominant crystal grain nucleation originates from regions overlying the S/D electrodes. As a result, an organic semiconductor channel is formed, interposed between the S/D electrodes.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: August 12, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Kanan Puntambekar, Lisa Stecker, Kurt Ulmer
  • Patent number: 8798280
    Abstract: The present publication describes a calibration method and apparatus, in which an electrical calibration signal is formed, an audio signal is formed in the loudspeaker from the calibration signal, the response of the audio signal is measured and analyzed, and the system is adjusted on the basis of the measurement results. The calibration signal is formed in the loudspeaker in such a way that it is essentially a sinusoidal signal, the frequency of which scans at least substantially through the entire audio frequency range.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: August 5, 2014
    Assignee: Genelec Oy
    Inventors: Andrew Goldberg, Aki Makivirta, Jussi Tikkanen, Juha Urhonen
  • Patent number: 8796662
    Abstract: A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: August 5, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Ho Song, Chan-Jin Park, In-Gyu Baek
  • Patent number: 8792659
    Abstract: A method of adjusting a signal processing parameter for a first hearing aid and a second hearing aid forming parts of a binaural hearing aid system to be worn by a user is provided. The binaural hearing aid system comprises a user specific model representing a desired asymmetry between a first ear and a second ear of the user. The method includes detecting a request for processing a parameter change at the first hearing aid, adjusting the signal processing parameter in the first hearing aid, and adjusting a processing parameter for the second hearing aid based on the request for processing parameter change and the user specific model.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: July 29, 2014
    Assignee: GN Resound A/S
    Inventors: Alexander Ypma, Aalbert de Vries, Joseph Renier Gerardus Maria Leenen, Job Geurts
  • Patent number: 8791514
    Abstract: An apparatus and method to decrease light saturation in a photosensor array and increase detection efficiency uses a light distribution profile from a scintillator-photodetector geometry to configure the photosensor array to have a non-uniform sensor cell pattern, with varying cell density and/or varying cell size and shape. A solid-state photosensor such as a SiPM sensor having such a non-uniform cell structure realizes improved energy resolution, higher efficiency and increased signal linearity. In addition the non-uniform sensor cell array can have improved timing resolution due to improvements in statistical fluctuations. A particular embodiment for such photosensors is in PET medical imaging.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: July 29, 2014
    Assignees: Siemens Medical Solutions USA, Inc., Siemens Aktiengesellschaft
    Inventors: Debora Henseler, Ronald Grazioso, Nan Zhang
  • Patent number: 8786174
    Abstract: An organic light emitting display device includes a substrate in which a first pixel area and a second pixel area different from each other are defined, a first electrode, a pixel defining layer, a common layer, a first surface processing layer, a second surface processing layer, a first liquid solution layer, a second liquid solution layer, and a second electrode. The first surface processing layer has a first width and is correspondingly included in the first pixel area. The second surface processing layer has a second width different from the first width and is correspondingly included in the second pixel area. The first liquid solution layer has the first width, and the second liquid solution layer has the second width. The first and second liquid solution layers have the same volume and different thicknesses.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: July 22, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young Il Kim, Euigyu Kim, Arong Lee
  • Patent number: 8785219
    Abstract: The present application provides a method of manufacturing an optoelectronic semiconductor device, comprising the steps of: providing a substrate; forming an optoelectronic system on the substrate; forming a barrier layer on the optoelectronic system; forming an electrode on the barrier layer; and annealing the optoelectronic semiconductor device; wherein the optoelectronic semiconductor device has a first forward voltage before the annealing step and has a second forward voltage after the annealing step, and a difference between the second forward voltage and the first forward voltage is smaller than 0.2 Volt.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: July 22, 2014
    Assignee: Epistar Corporation
    Inventors: Tz Chiang Yu, Jenn Hwa Fu, Hsin Hsiung Huang
  • Patent number: 8785763
    Abstract: Nanostructures are joined using one or more of a variety of materials and approaches. As consistent with various example embodiments, two or more nanostructures are joined at a junction between the nanostructures. The nanostructures may touch or be nearly touching at the junction, and a joining material is deposited and nucleates at the junction to couple the nanostructures together. In various applications, the nucleated joining material facilitates conductivity (thermal and/or electric) between the nanostructures. In some embodiments, the joining material further enhances conductivity of the nanostructures themselves, such as by growing along the nanostructures and/or doping the nanostructures.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: July 22, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Melburne C. LeMieux, Ajay Virkar, Zhenan Bao
  • Patent number: 8785946
    Abstract: A high quality single crystal wafer of SiC is disclosed having a diameter of at least about 3 inches and a 1 c screw dislocation density from about 500 cm?2 to about 2000 cm?2.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: July 22, 2014
    Assignee: Cree, Inc.
    Inventors: Adrian Powell, Mark Brady, Stephan G. Mueller, Valeri F. Tsvetkov, Robert T. Leonard
  • Patent number: 8779429
    Abstract: RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: July 15, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: O-Sung Seo, Hwa-Yeul Oh, Hyoung-Cheol Lee, Tae-Kyung Yim
  • Patent number: 8772813
    Abstract: Provided is an LED package. It is easy to control luminance according to the luminance and an angle applicable. Since heat is efficiently emitted, the LED package is easily applicable to a high luminance LED. The manufacturing process is convenient and the cost is reduced. The LED package includes a substrate, an electrode, an LED, and a heatsink hole. The electrode is formed on the substrate. The LED is mounted in a side of the substrate and is electrically connected to the electrode. The heatsink hole is formed to pass through the substrate, for emitting out heat generated from the LED.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 8, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Wan Ho Kim
  • Patent number: 8772766
    Abstract: An organic EL display device of active matrix type wherein insulated-gate field effect transistors formed on a single-crystal semiconductor substrate are overlaid with an organic EL layer; characterized in that the single-crystal semiconductor substrate (413 in FIG. 4) is held in a vacant space (414) which is defined by a bed plate (401) and a cover plate (405) formed of an insulating material, and a packing material (404) for bonding the bed and cover plates; and that the vacant space (414) is filled with an inert gas and a drying agent, whereby the organic EL layer is prevented from oxidizing.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 8772748
    Abstract: A semiconductor memory device includes a first conductive line, a second conductive line, a cell unit, a silicon nitride film and a double-sidewall film. The first conductive line extends in a first direction. The second conductive line extends in a second direction crossing the first direction. The cell unit includes a phase-change film and a rectifier element connected in series with each other between the first conductive line and the second conductive line. The silicon nitride film is formed on a side surface of the phase-change film. The double-sidewall film includes a silicon oxide film and the silicon nitride film formed on a side surface of the rectifier element.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: July 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuaki Yasutake
  • Patent number: 8772828
    Abstract: A semiconductor device includes a semiconductor material disposed in a trench with polysilicon lining at least the bottom of the trench. The semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: July 8, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hong Chang, John Chen
  • Patent number: 8766318
    Abstract: The objective is to improve capabilities such as high-speed switching of a compound semiconductor device. Provided is a semiconductor wafer comprising a silicon wafer; an insulating film that is formed on the silicon wafer and that has an open portion reaching the silicon wafer; a Ge crystal formed in the open portion; a seed compound semiconductor crystal that is grown with the Ge crystal as a nucleus and that protrudes beyond a surface of the insulating film; and a laterally grown compound semiconductor layer that is laterally grown on the insulating film with a specified surface of the seed compound semiconductor crystal as a seed surface.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Masahiko Hata, Tomoyuki Takada
  • Patent number: 8759820
    Abstract: An object is to provide a transistor in which light deterioration is suppressed as much as possible and electrical characteristics are stable, and a semiconductor device including the transistor. The attention focuses on the fact that light is reflected by a film used for forming a transistor and multiple interaction occurs. When the optical thickness of the film which causes the reflection is roughly an odd multiple of ?0/4 or roughly an even multiple of ?0/4, reflectance in a wavelength region of light which is absorbed by an oxide semiconductor is increased without a loss of a function of the film with respect to the transistor, whereby the amount of light absorbed by the oxide semiconductor is reduced and an effect of reducing light deterioration is increased.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Keisuke Murayama
  • Patent number: 8754392
    Abstract: One embodiment of the disclosure can provide a storage layer of a resistive memory element comprising a resistance changeable material. The resistance changeable material can include carbon. Contact layers can be provided for contacting the storage layer. The storage layer can be disposed between a bottom contact layer and a top contact layer. The resistance changeable material can be annealed at a predetermined temperature over a predetermined annealing time for rearranging an atomic order of the resistance changeable material.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Daniele Caimi, Evangelos S. Eleftheriou, Charalampos Pozidis, Christophe P. Rossel, Abu Sebastian
  • Patent number: 8754416
    Abstract: The present invention provides a method of an active-matrix thin film transistor array, comprising of two levels of metallic interconnections formed from one layer of metallic conductor; and thin-film transistors with source, drain and gate electrodes either fully or partially replaced with metal, and wherein the pixel electrodes are polycrystalline silicon.
    Type: Grant
    Filed: November 24, 2006
    Date of Patent: June 17, 2014
    Assignee: The Hong Hong University of Science and Technology
    Inventors: Hoi-Sing Kwok, Man Wong, Zhiguo Meng, Dongli Zhang, Jiaxin Sun, Xiuling Zhu
  • Patent number: 8754413
    Abstract: An X-ray detection device includes a gate electrode and a lower electrode on a substrate and laterally spaced from each other, a dielectric layer covering the gate electrode and the lower electrode, and a conductive pattern on the dielectric layer at a side of the gate electrode adjacent to the lower electrode and overlapping the lower electrode. The device also includes a source electrode spaced apart from the conductive pattern that is on the dielectric layer at the other side of the gate electrode, and an interlayer insulation layer covering the conductive pattern and the source electrode. A collector electrode, a photoelectric conversion layer, and a bias electrode are sequentially stacked on the interlayer insulation layer.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: June 17, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Kyung Soo Lee
  • Patent number: 8754442
    Abstract: A silicon on insulator N type semiconductor device, includes a N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer; and an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: June 17, 2014
    Assignee: Southeast University
    Inventors: Longxing Shi, Qinsong Qian, Changlong Huo, Weifeng Sun, Shengli Lu