Abstract: Memory cells and methods of forming the same and devices including the same. The memory cells have first and second electrodes. An amorphous semiconductor material capable of electronic switching and having a first band gap is between the first and second electrodes. A material is in contact with the semiconductor material and having a second band gap, the second band gap greater than the first band gap.

Abstract: Solid state lighting (SSL) devices including a plurality of SSL emitters and methods for manufacturing SSL devices are disclosed. Several embodiments of SSL devices in accordance with the technology include a support having a first lead and a second lead, a plurality of individual SSL emitters attached to the support, and a plurality of lenses. Each SSL emitter has a first contact electrically coupled to the first lead of the support and a second contact electrically coupled to the second lead of the support such that the SSL emitters are commonly connected. Each lens has a curved surface and is aligned with a single corresponding SSL emitter.

Abstract: The invention relates to a method for adapting sound pressure levels in at least one listening location, the sound pressure being generated by a first and a second loudspeaker, each loudspeaker having a supply channel arranged upstream thereto, where at least the supply channel of the second loudspeaker modifies the phase of an audio signal transmitted therethrough according to a phase function. The method includes supplying an audio signal to the supply channels and thus generating an acoustic sound signal; measuring the acoustic sound signal at each listening location and providing corresponding electrical signals representing the measured acoustic sound signal; estimating updated transfer characteristics for each pair of loudspeaker and listening location; calculating an optimum offset phase function based on a mathematical model using the estimated transfer characteristics; updating the phase function by superposing the optimal offset phase function thereto.

Abstract: A method and apparatus for polarity detection. The method includes applying a band-pass filter to an impulse response of a loudspeaker, applying an exponential weighting to the band-pass filtered impulse response, wherein the exponential decay parameter is related to the higher corner frequency of the band-pass filter, finding the maximum peak in a waveform of sampled impulse responses, and detecting the connection polarity of the maximum peak as the polarity of the peak.

Abstract: Methods for combinatorially processing semiconductor substrates are provided. The methods may involve receiving a substrate into a combinatorial processing chamber and sealing a plurality of flow cells against a surface of the substrate. The plurality of flow cells is enclosed within the combinatorial processing chamber to define an enclosed external environment for the plurality of flow cells. A pressure differential is created between a reaction area of the plurality of flow cells of the combinatorial processing chamber and the external environment, wherein each flow cells of the plurality of flow cells defines a site isolating region of the substrate. The regions the substrate are then combinatorially processed.

Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.

Abstract: An assembly includes a dielectric layer in contact with a semiconductor layer. The dielectric layer includes a crosslinked polymeric material having isocyanurate groups, wherein the dielectric layer is free of zirconium oxide particles. The semiconductor layer includes a non-polymeric organic semiconductor material, and is substantially free of electrically insulating polymer. Electronic components and devices including the assembly are also disclosed.

Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film.

Abstract: An organic light emitting display apparatus in which image quality can be improved. The organic light emitting display apparatus includes: a substrate; a first electrode disposed on the substrate; a pixel definition layer formed on the first electrode and having an opening portion through which a region of the first electrode is exposed; an intermediate layer connected to the first electrode through the opening portion and including an organic emission layer; a second electrode electrically connected to the intermediate layer; and an inorganic planarization pattern portion disposed between the substrate and the first electrode and formed to at least correspond to the opening portion.

Abstract: The invention relates to a method and a device for the plasma treatment of metal substrates or insulating substrates (3) running substantially continuously through a vacuum chamber having a treatment zone (2), the plasma being sustained by radiofrequency inductive coupling in the treatment zone (2) by means of an inductor (4) connected to a radiofrequency generator, in which the inductor (4) is protected from any contamination by the material emitted by the surface of the substrates (3) by means of a Faraday cage (7), which is positioned between the plasma and the inductor (4), and in which the Faraday cage (7) is on average electrically biassed positively with respect to the substrates (3) or with respect to a counter-electrode present in the plasma.

Abstract: According to an example embodiment, a power electronic device includes a first semiconductor layer, a second semiconductor layer on a first surface of the first semiconductor layer, and a source, a drain, and a gate on the second semiconductor layer. The source, drain and gate are separate from one another. The power electronic device further includes a 2-dimensional electron gas (2DEG) region at an interface between the first semiconductor layer and the second semiconductor layer, a first insulating layer on the gate and a second insulating layer adjacent to the first insulating layer. The first insulating layer has a first dielectric constant and the second insulating layer has a second dielectric constant less than the first dielectric constant.

Abstract: A Schottky contact is disposed atop the surface of the semiconductor. A first Schottky contact metal layer is disposed atop a first portion of the semiconductor surface. A second Schottky contact metal is disposed atop a second portion of the surface layer and joins the first Schottky contact metal layer. A first. Schottky contact metal layer has a lower work function than the second Schottky contact metal layer.

Abstract: A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode on the semiconductor layer, a drain electrode opposing the source electrode with respect to the gate electrode, and a data line; a passivation layer on the data wire having a contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole. The gate wire has a first region and second region where the gate line and the gate electrode are positioned, respectively. The thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a variable resistive pattern, a lower electrode structure, a heating electrode. The heating electrode includes first, second and plate portions. The first portion is extended in a first direction. The second portion is upwardly protruded from a central region of a top surface of the first portion and is in contact with the variable resistive pattern. The plate portion is extended from a lower end of the first portion in a second direction perpendicular to the first direction. The plate portion is in contact with the lower electrode structure.

Abstract: A light emitting device includes a serially-connected LED array of a plurality of LED cells epitaxially formed on a substrate. The LED array includes a first LED cell, and a second LED cell adjacent to each other, and a serially-connected LED sub-array including at least three LED cells intervening the first and the second LED cells. Each LED cell includes a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer; and an active layer formed between the first semiconductor layer and the second semiconductor layer; wherein the distance between the first semiconductor layer of the first LED cell and that of the second LED cell is larger than 30 ?m, and one of the first semiconductor layers and/or one of the second semiconductor layers of the LED cells includes a round corner with a radius of curvature not less than 15 ?m.

Abstract: A light-emitting device includes an element mounting substrate, a light-emitting element on the element mounting substrate, a case formed around the light-emitting element and having an opening on a light extraction side of the light-emitting device, and a sealing material filled in the opening of the case to seal the light-emitting element. The element mounting substrate includes an uneven portion configured to firmly attach the element mounting substrate to the case or the sealing material.

Abstract: A light-emitting diode (LED) device is provided. The LED device has a lower LED layer and an upper LED layer with a light-emitting layer interposed therebetween. A current blocking layer is formed in the upper LED layer such that current passing between an electrode contacting the upper LED layer flows around the current blocking layer. When the current blocking layer is positioned between the electrode and the light-emitting layer, the light emitted by the light-emitting layer is not blocked by the electrode and the light efficiency is increased. The current blocking layer may be formed by converting a portion of the upper LED layer into a resistive region. In an embodiment, ions such as magnesium, carbon, or silicon are implanted into the upper LED layer to form the current blocking layer.

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Abstract: A method is provided for fabricating a printed organic thin film transistor (OTFT) with a patterned organic semiconductor using a fluropolymer banked crystallization well. In the case of a bottom gate OTFT, a substrate is provided and a gate electrode is formed overlying the substrate. A gate dielectric is formed overlying the gate electrode, and source (S) and drain (D) electrodes are formed overlying the gate dielectric. A gate dielectric OTFT channel interface region is formed between the S/D electrodes. A well with fluropolymer containment and crystallization banks is then formed, to define an organic semiconductor print area. The well is filled with an organic semiconductor, covering the S/D electrodes and the gate dielectric OTFT channel interface. Then, the organic semiconductor is crystallized. Predominant crystal grain nucleation originates from regions overlying the S/D electrodes. As a result, an organic semiconductor channel is formed, interposed between the S/D electrodes.

Abstract: In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.