Patents Examined by Minh Loan Tran
  • Patent number: 10777772
    Abstract: A panel comprises a substrate, a semiconductor layer on the substrate, and including an oxide semiconductor or a low-temperature polycrystalline silicon, an interlayer insulating film on the substrate and the semiconductor layer, a passivation layer on the interlayer insulating film, an overcoat layer on the passivation layer, a light emitting layer on the overcoat layer, and an encapsulation layer on the light emitting layer. The encapsulation layer includes an auxiliary encapsulation layer having at least one of a silicon nitride (SiNx:H) layer including hydrogen, a silicon oxide (SiO2:H) layer including hydrogen, or a silicon oxynitride (SiON:H) layer including hydrogen. At least one of the interlayer insulating film, the passivation layer, or the overcoat layer is a hydrogen trapping layer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 15, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Jiyong Noh, PilSang Yun, SeHee Park, JungSeok Seo
  • Patent number: 10770582
    Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, a first p+-type region, and a second p+-type region are provided. A metal film of a trench SBD is connected to a source electrode; and a p+-type region is provided between the source electrode and the p-type base layer.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Naoki Kumagai
  • Patent number: 10770581
    Abstract: A first side wall and a second side wall of a trench are each an a-plane having high carrier mobility. Along the first side wall of the trench, a gate insulating film is provided. A gate electrode is provided in the trench, and across the gate insulating film, opposes a portion of a p-type base region between an n+-type source region and an n-type current spreading region. Along the second side wall of the trench, a conductive layer is provided. The conductive layer, at the second side wall of the trench, forms Schottky contacts with a p++-type contact region, the p-type base region, and the n-type current spreading region. The trench has a bottom corner portion that is at the second side wall and encompassed by a p+-type region that is provided in the n-type current spreading region so as to be separated from the p-type base region.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada, Naoki Kumagai
  • Patent number: 10756164
    Abstract: A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: August 25, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 10741496
    Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over a semiconductor substrate, a source electrode and a drain electrode formed over the semiconductor substrate within openings formed in the first dielectric layer, a gate electrode formed over the semiconductor substrate between the source electrode and the drain electrode, and a protection layer disposed on the source electrode, the drain electrode, and the first dielectric layer, wherein a first edge of the protection layer terminates the protection layer between the source electrode and the gate electrode, and a second edge of the protection layer terminates the protection layer between the gate electrode and the drain electrode. A method for fabricating the semiconductor devices includes forming a first dielectric layer over the semiconductor substrate, forming source and drain electrodes, depositing the protection layer over the source and drain electrodes, and forming the gate electrode.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: August 11, 2020
    Assignee: NXP USA, Inc.
    Inventors: Jenn Hwa Huang, James Allen Teplik, Darrell Glenn Hill
  • Patent number: 10741545
    Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 11, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Masaki Tamaru, Kazuma Yoshida, Michiya Otsuji, Tetsuyuki Fukushima
  • Patent number: 10734551
    Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: August 4, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Patent number: 10727381
    Abstract: A light emitting device according to one embodiment of the present disclosure includes a light emitting element, a fluorescent material layer, a reflective film, a light-transmissive member, and an absorbing layer. The light emitting element emits first light. The fluorescent material layer is disposed on the light emitting element. The fluorescent material layer is excited by the first light to emit second light being longer in wavelength than the first light. The reflective film is disposed on the fluorescent material layer to reflect part of the first light and transmit the second light. The light-transmissive member is disposed on the reflective film. The absorbing layer is disposed on the light-transmissive member to absorb part of the first light. The light emitting element is identical in area to or smaller in area than the fluorescent material layer in a plan view.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: July 28, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Taiki Yuasa
  • Patent number: 10727243
    Abstract: A 3D memory device includes a multi-layers stacking structure having a plurality of conductive layers and insulating layers stacked in a staggered manner, at least one trench passing through the conductive layers and a plurality of recess regions extending into the conductive layers from the trench; a dielectric blocking strip lining sidewalls of the trench and the recess regions; a plurality of floating gates disposed in the recess regions and isolated from the conductive layers by the dielectric blocking strip; a dielectric strip overlies sidewalls of the floating gates exposed from the recess regions; a semiconductor strip disposed in the trench, insulated from the floating gates by the dielectric strip, and includes a first doping region, a second doping region and a channel region disposed between and connects to the first doping region and the second doping region, and overlapping with the floating gates.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: July 28, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting Lue, Wei-Chen Chen
  • Patent number: 10710781
    Abstract: A resealable cover for a beverage container that holds a carbonated beverage. The cover includes a base engageable with a rim of the container and a lid movable between an open and closed position relative to the base. When in the closed position, a passageway is defined between a portion of the lid and a portion of the base. The passageway permits fluid communication between air surrounding an exterior surface of the cover and a space defined between the lid and an opening in the container. Pressure that builds up under the lid from gas escaping from the liquid may be relieved by outgassing through the passageway. The cover includes latches on the base that engage in notches on the lid to help lock the lid in place. The lid is rotated relative to the base to release the latches and permit the lid to be opened.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: July 14, 2020
    Inventor: William Battaglia
  • Patent number: 10714547
    Abstract: Provided is a light emitting display apparatus including a first substrate, a first electrode on the first substrate, a bank layer having an opening exposing a portion of the first electrode layer, a bank recess depressed on the bank layer, a second electrode layer on the first electrode layer and the bank layer, and a cover layer covering a lower surface and an inner side surface of the bank recess.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: July 14, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Joonyoung Heo
  • Patent number: 10707370
    Abstract: A photoelectric sensor capable of saving a space is provided. A photoelectric sensor includes a case body with a substantially rectangular parallelepiped shape that accommodates at least one of a light projecting section and a light receiving section. The case body has a front surface that has a light projecting and receiving surface that allows at least one of light from the light projecting section and light to the light receiving section to pass therethrough and a rear surface that is located on a side opposite to the front surface, and a cable that accommodates cords that are connected to at least one of the light projecting section and the light receiving section via a control section is attached to the rear surface.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: July 7, 2020
    Assignee: OMRON Corporation
    Inventors: Hiroyuki Mizusaki, Tsuyoshi Miyata, Makoto Sugimoto, Jumpei Nakamura, Tomohiro Tsuji
  • Patent number: 10700048
    Abstract: A light-emitting diode (LED) projector includes an LED display panel and a projection lens arranged in front of LED display panel and configured to collect and project light emitted by the LED display panel. The LED display panel includes an LED panel and a micro lens array arranged over the LED panel. The LED panel includes a substrate, a driver circuit array on the substrate and including a plurality of pixel driver circuits arranged in an array, and an LED array including a plurality of LED dies each being coupled to one of the pixel driver circuits. The micro lens array includes a plurality of micro lenses each corresponding to and being arranged over at least one of the LED dies.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 30, 2020
    Assignee: Hong Kong Beida Jade Bird Display Limited
    Inventors: Lei Zhang, Fang Ou, Qiming Li
  • Patent number: 10693050
    Abstract: A light emitting device can include a substrate including a top surface, an outermost side surface, and a bottom surface; a light emitting diode chip on the top surface of the substrate; a reflecting member disposed on a first portion of the top surface of the substrate and the reflecting member having a cavity; a first metal layer disposed on a second portion of the top surface, one side of the outermost side surface, and a first portion of the bottom surface; a second metal layer disposed on a third portion of the top surface, another side of the outermost side surface, and a second portion of the bottom surface; a heatsink disposed on the bottom surface of the substrate; and at least two heatsink holes in the substrate formed to pass through the substrate, in which the at least two heatsink holes are in contact with the heatsink, and a reflective material is on an inside surface of the at least two heatsink holes, the first metal layer, the second metal layer, and the heatsink are separated from each other
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 23, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Wan Ho Kim
  • Patent number: 10692968
    Abstract: Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: June 23, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Min Lee, Jongryul Jun, Eun A Kim, Jung-Bum Lim
  • Patent number: 10686078
    Abstract: A semiconductor structure and fabrication method are provided. The method includes: providing a substrate; forming first fins on the substrate; forming barrier layers covering sidewalls of the first fins; forming a first groove in each first between the adjacent first barrier layers; and forming a first inner epitaxial layer in each first groove. The first fin and the adjacent first barrier layers surround the corresponding first groove.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10665728
    Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 26, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Masatoshi Aketa, Yuta Yokotsuji
  • Patent number: 10665596
    Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Steven Alan Lytle
  • Patent number: 10665736
    Abstract: An infrared light receiving device includes: a structure having a supporting base and a laminate body, the laminate body including a first superlattice layer, a second superlattice layer and a semiconductor region, the first superlattice layer, the second superlattice layer and the semiconductor region being arranged sequentially on the supporting base, and the laminate body having an array of semiconductor mesas for photodiodes and a recess defining the array of semiconductor mesas; and a first electrode connected to the first superlattice layer. The first superlattice layer has an n-type conductivity. The semiconductor region has a p-type conductivity. The first superlattice layer has a type-II superlattice structure and forming a heterojunction with the supporting base. The recess has first and second recess portions. The second recess portion has a bottom in the first superlattice layer. The first recess portion has a depth larger than that of the second recess portion.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 26, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Daisuke Kimura, Sundararajan Balasekaran
  • Patent number: 10658374
    Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang