Patents Examined by Minh Loan Tran
  • Patent number: 10468613
    Abstract: Embodiment of the present disclosure provides a motherboard of flexible display panel, a cutting method thereof, a flexible display panel and a display device. The motherboard of flexible display panel includes: a plurality of display units; a space region, disposed to at least separate adjacent ones of the display unis; and a barrier strip, disposed in the space region and configured to stop a crack from extending towards the display units across the barrier strip.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: November 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongwei Tian, Yanan Niu, Yueping Zuo
  • Patent number: 10468433
    Abstract: A three-dimensional semiconductor device is provided including main separation structures disposed on a substrate, and extending in a first direction, parallel to a surface of the substrate; gate electrodes disposed between the main separation structures; a first secondary separation structure penetrating through the gate electrodes, between the main separation structures, and including a first linear portion and a second linear portion, having end portions opposing each other; and second secondary separation structures disposed between the first secondary separation structure and the main separation structures, and penetrating through the gate electrodes. The second secondary separation structures have end portions opposing each other between the second linear portion and the main separation structures.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Soo Kim, Young Jin Jung, Jae Duk Lee
  • Patent number: 10461222
    Abstract: A light-emitting element includes: a sapphire substrate having a c-plane at a main surface thereof; and a semiconductor layer provided at the main surface side of the sapphire substrate. The sapphire substrate includes a first unit including a first region, a second region, and a third region, wherein, when viewed from the main surface side, the three regions together have a shape of a regular hexagon that is evenly divided into the three regions such that each region has a shape of a rhombus; and a plurality of second units disposed to be aligned with each side of the first unit, the second unit having mirror symmetry relative to the first unit. The first unit and the second units are arranged to make a space at the center of the unit.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: October 29, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Makoto Abe, Keisuke Higashitani, Naoki Azuma, Akiyoshi Kinouchi
  • Patent number: 10461064
    Abstract: Flip chip LEDs comprise a transparent carrier and an active material layer such as AlInGaP bonded to the carrier and that emits light between about 550 to 650 nm. The flip chip LED has a first electrical terminal in contact with a first region of the active material layer, and a second electrical terminal in contact with a second region of the active material layer, wherein the first and second electrical terminals are positioned along a common surface of the active material layer. Chip-on-board LED packages comprise a plurality of the flip chip LEDs with respective first and second electrical terminals interconnected with one another. The package may include Flip chip LEDs that emit light between 420 to 500 nm, and the flip chip LEDs are covered with a phosphorus material comprising a yellow constituent, and may comprise a transparent material disposed over the phosphorus material.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 29, 2019
    Assignee: Bridgelux, Inc.
    Inventor: Vladimir A. Odnoblyudov
  • Patent number: 10453831
    Abstract: The invention provides a punching packaged light-emitting diode apparatus, which comprises: a substrate, including a first molding material, a first nano heat conductive material, and a first fluorescent material; a light-emitting unit, located on a surface of the substrate; two wiring units, individually connected to the light-emitting unit; and a packaging material, including a second molding material, a high refractive material, a second nano heat conductive material, and a second fluorescent material, to cover the wiring units and the light-emitting unit in a solidified structure formed by a punching process; wherein, the light-emitting unit emits light to outside through the substrate and the packaging material.
    Type: Grant
    Filed: June 24, 2018
    Date of Patent: October 22, 2019
    Inventor: Guan-Jie Luo
  • Patent number: 10453999
    Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 22, 2019
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Patent number: 10446610
    Abstract: An electronic device may include a semiconductor memory. The semiconductor memory may include a stack in which a plurality of dielectric layers and a plurality of first electrodes are alternately stacked over a substrate in a vertical direction relative to the substrate; a hole pattern passing through the stack in the vertical direction and having a polygonal shape when viewed in a plan view; a plurality of second electrodes disposed on respective sidewalls of the hole pattern; and a plurality of variable resistance layers interposed between the plurality of second electrodes and the plurality of horizontal electrodes.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: October 15, 2019
    Assignee: SK HYNIX INC.
    Inventor: Kyung-Wan Kim
  • Patent number: 10437087
    Abstract: A display device includes a first flexible substrate on which a display region and a peripheral region located along a periphery of the display region are arranged; a connection terminal provided in the peripheral region, the connection terminal being connected with an integrated circuit; and a first insulating film in contact with the first flexible substrate. The first insulating film is present in the display region, and the first insulating film is not present between the connection terminal and the first flexible substrate.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: October 8, 2019
    Assignee: Japan Display Inc.
    Inventors: Yosuke Hyodo, Shinichiro Oka, Lu Jin
  • Patent number: 10424748
    Abstract: A flexible display panel, a manufacturing method thereof and a flexible display device, which relate to the technical field of flexible display and reduce the probability of the occurrence of cracks on an inorganic encapsulation structure when a flexible display panel is bent, so that the service life of light emitting devices in the flexible display substrate is prolonged. The flexible display panel includes a flexible display substrate and an encapsulation structure arranged on a surface of the flexible display substrate. A portion of the encapsulation structure corresponding to a non-display region is an inorganic encapsulation structure. The flexible display panel further includes an organic encapsulation layer covering the inorganic encapsulation structure. The manufacturing method of a flexible display panel manufacture the flexible display panel described in the above technical solutions. The flexible display panel provided by the present disclosure is used in a flexible display device.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: September 24, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Peng Cai, Ping Song, Youwei Wang, Jing Yang
  • Patent number: 10418513
    Abstract: A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein the first crack surface is inclined to the first deteriorated surface or the second deteriorated surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 17, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chia Chen Tsai, Chen Ou, Chi Ling Lee, Chi Shiang Hsu
  • Patent number: 10418447
    Abstract: Provided is a thin film transistor, a production method thereof, and an electronic apparatus. The thin film transistor comprises a substrate, and a gate electrode, a gate insulator layer, a source electrode, a drain electrode and an active layer on the substrate, wherein the active layer comprises a stack of two or more layers of graphene-like two-dimensional semiconductor material. The electronic apparatus comprises the thin film transistor, and may be used as an optical or mechanical sensor.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: September 17, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Guangyao Li, Guangcai Yuan, Dongfang Wang, Jun Wang, Qinghe Wang, Ning Liu
  • Patent number: 10411067
    Abstract: Techniques are disclosed for forming a monolithic integrated circuit semiconductor structure that includes a radio frequency (RF) frontend portion and may further include a CMOS portion. The RF frontend portion includes componentry implemented with column III-N semiconductor materials such as gallium nitride (GaN), indium nitride (InN), aluminum nitride (AlN), and compounds thereof, and the CMOS portion includes CMOS logic componentry implemented with semiconductor materials selected from group IV of the periodic table, such as silicon, germanium, and/or silicon germanium (SiGe). Either of the CMOS or RF frontend portions can be native to the underlying substrate to some degree. The techniques can be used, for example, for system-on-chip integration of III-N transistors and/or RF filters, along with column IV CMOS devices on a single substrate.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10409120
    Abstract: A display panel and a display device are provided. The display panel includes a first substrate having a step area; a second substrate disposed opposite to the first substrate, wherein the second substrate has a first surface facing the first substrate and an opposite second surface; a Chip On Flex (COF) disposed on the step area of the first substrate and including at least one ground pad; a conductive layer disposed on the second surface of the second substrate; and a conductive adhesive electrically connected to the conductive layer and the at least one ground pad.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: September 10, 2019
    Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
    Inventors: Guochang Lai, Hongbo Zhou, Huangyao Wu, Zhongjie Zhang, Qiongqin Mao
  • Patent number: 10396244
    Abstract: A nitride semiconductor light emitting element comprises a sapphire substrate, and a light emitting element structure portion that has a plurality of nitride semiconductor layers formed on the sapphire substrate. The nitride semiconductor light emitting element is a back-surface-emitting type nitride semiconductor light emitting element that outputs light from the light emitting element structure portion to an outside of the element through the sapphire substrate. The nitride semiconductor light emitting element is divided into a chip whose planarly-viewed shape is a square or a rectangle. A thickness of the sapphire substrate is 0.45 to 1 times an average length of sides of the planarly-viewed shape of the chip.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 27, 2019
    Assignee: SOKO KAGAKU CO., LTD.
    Inventors: Akira Hirano, Cyril Pernot, Tetsuhiko Inazu
  • Patent number: 10396148
    Abstract: A semiconductor layer arranged on a semiconductor substrate includes an active region and an element isolation region that surrounds the first active region when viewed in plan. A field effect transistor is formed in the active region. A plurality of guard ring electrodes separated from each other affect a potential of the active region through the element isolation region. An interlayer insulating film is formed over the semiconductor layer, the field effect transistor, and the guard ring electrodes. At least one guard ring connection wiring formed on the interlayer insulating film electrically interconnects the plurality of guard ring electrodes.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 27, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinnosuke Takahashi, Masayuki Aoike
  • Patent number: 10396030
    Abstract: A semiconductor device includes a first electrode which includes a first main portion, and a first extension that extends from the first main portion, and a dielectric layer which surrounds a sidewall and a bottom surface of the first main portion, wherein the first main portion includes a first portion having a first depth, and a second portion having a second depth deeper than the first depth.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Nyung Lee, Jeong Hoon Ahn
  • Patent number: 10396189
    Abstract: Considering ease of electrical conduction tests and the like, electrodes provided mainly above an active region are desirably continuous on a single plane. A semiconductor device is provided, including: a semiconductor substrate; a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein the second top surface electrode has: a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and a second connecting portion that connects the first region and the second region above the first connecting portion.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: August 27, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10388623
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: August 20, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Patent number: 10388678
    Abstract: A method for manufacturing a gate structure includes: forming a buffer layer on a lateral surface of a substrate; forming a groove on the buffer layer, where the groove penetrates the buffer layer; forming a gate in the groove, where an upper surface of the gate and an upper surface of the buffer layer are located on a same plane; forming an insulating layer on the upper surface of the gate and the upper surface of the buffer layer; forming, on an upper surface of the insulating layer, a semiconductor layer disposed opposite the gate; and forming, on an upper surface of the semiconductor layer and/or the upper surface of the insulating layer, a data line partially overlapping the semiconductor layer. A display device is further disclosed. The display device includes a gate structure.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 20, 2019
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chung-Kuang Chien
  • Patent number: 10374054
    Abstract: A ferroelectric memory device includes a substrate having a source electrode and a drain electrode therein, a first interfacial dielectric layer including an anti-ferroelectric material disposed on the substrate between the source electrode and the drain electrode, a ferroelectric gate dielectric layer including a ferroelectric material disposed on the first interfacial dielectric layer, and a gate electrode disposed on the ferroelectric gate dielectric layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo