Patents Examined by Minh Loan Tran
  • Patent number: 10665736
    Abstract: An infrared light receiving device includes: a structure having a supporting base and a laminate body, the laminate body including a first superlattice layer, a second superlattice layer and a semiconductor region, the first superlattice layer, the second superlattice layer and the semiconductor region being arranged sequentially on the supporting base, and the laminate body having an array of semiconductor mesas for photodiodes and a recess defining the array of semiconductor mesas; and a first electrode connected to the first superlattice layer. The first superlattice layer has an n-type conductivity. The semiconductor region has a p-type conductivity. The first superlattice layer has a type-II superlattice structure and forming a heterojunction with the supporting base. The recess has first and second recess portions. The second recess portion has a bottom in the first superlattice layer. The first recess portion has a depth larger than that of the second recess portion.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: May 26, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Daisuke Kimura, Sundararajan Balasekaran
  • Patent number: 10658374
    Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
  • Patent number: 10658485
    Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Han Lin, Shih-Chang Tsai, Wen-Shuo Hsieh, Te-Yung Liu
  • Patent number: 10644217
    Abstract: A quantum bit (qubit) flip chip assembly may be formed when a qubit it formed on a first chip and an optically transmissive path is formed on a second chip. The two chips may be bonded. The optically transmissive path may provide optical access to the qubit on the first chip.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Jason S. Orcutt, Martin O. Sandberg, Markus Brink, Vivekananda P. Adiga, Nicholas T. Bronn
  • Patent number: 10644252
    Abstract: A method of making a photodetector includes: providing a substrate and forming an interdigital electrode layer on a surface of the substrate; and forming a photoactive layer on a surface of the interdigital electrode layer.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: May 5, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hao-Ming Wei, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10636964
    Abstract: Embodiments of the disclosure provide methods for forming MTJ structures from a film stack disposed on a substrate for MRAM applications and associated MTJ devices. The methods described herein include forming the film properties of material layers from the film stack to create a film stack with a sufficiently high perpendicular magnetic anisotropy (PMA). An iron containing oxide capping layer is utilized to generate the desirable PMA. By utilizing an iron containing oxide capping layer, thickness of the capping layer can be more finely controlled and reliance on boron at the interface of the magnetic storage layer and the capping layer is reduced.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: April 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Lin Xue, Chi Hong Ching, Xiaodong Wang, Mahendra Pakala, Rongjun Wang
  • Patent number: 10634941
    Abstract: A display device includes a first flexible substrate on which a display region and a peripheral region located along a periphery of the display region are arranged; a connection terminal provided in the peripheral region, the connection terminal being connected with an integrated circuit; and a first insulating film in contact with the first flexible substrate. The first insulating film is present in the display region, and the first insulating film is not present between the connection terminal and the first flexible substrate.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 28, 2020
    Assignee: Japan Display Inc.
    Inventors: Yosuke Hyodo, Shinichiro Oka, Lu Jin
  • Patent number: 10622562
    Abstract: An illustrative method of fabricating a memory array structure includes: forming at least one access device layer on an upper surface of a first conductive layer, the access device layer being in electrical connection with the first conductive layer; forming a sacrificial layer on an upper surface of the access device layer; etching the access device layer and the sacrificial layer using a same masking feature to form an access device that is self-aligned with a portion of the sacrificial layer; replacing a portion of the sacrificial layer with memory storage material to form a storage element, a first terminal of the storage element being in electrical connection with the access device; and forming a second conductive layer on an upper surface of the storage element, a second terminal of the storage element being in electrical connection with the second conductive layer.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 14, 2020
    Assignee: International Business Machines Corporation
    Inventor: Matthew J. BrightSky
  • Patent number: 10618804
    Abstract: A method of manufacturing a semiconductor structure includes receiving a substrate, receiving a heater, receiving an electrode, and receiving a sensing material. The substrate have a first surface, a second surface opposite to the first surface and a plurality of vias extending from the second surface toward the first surface and filled with a conductive or semiconductive material and a first oxide layer, the first oxide layer surrounding the conductive or semiconductive material in the plurality of vias, and a second oxide layer disposed over the first surface and the second surface. The heater is disposed within a membrane over the first surface of the substrate and electrically connected with the substrate. The electrode is over the heater and the membrane; and the sensing material covers a portion of the electrode.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu, Fei-Lung Lai, Shiang-Chi Lin
  • Patent number: 10608144
    Abstract: Provided is a light emitting diode (LED) mounted on a carrier substrate and including a semiconductor epitaxial structure and at least one electrode pad structure. The semiconductor epitaxial structure is electrically connected to the carrier substrate. The electrode pad structure includes a eutectic layer, a barrier layer and a ductility layer. The eutectic layer is adapted for eutectic bonding to the carrier substrate. The barrier layer is between the eutectic layer and the semiconductor epitaxial structure. The barrier layer blocks the diffusion of the material of the eutectic layer in the eutectic bonding process. The ductility layer is between the eutectic layer and the semiconductor epitaxial structure. The ductility layer reduces the stress on the LED produced by thermal expansion and contraction of the substrate during the eutectic bonding process, so as to prevent the electrode pad structure from cracking, and maintain the quality of the LED.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: March 31, 2020
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Chih-Ming Shen, Sheng-Tsung Hsu, Kuan-Chieh Huang, Jing-En Huang, Shao-Ying Ting
  • Patent number: 10593628
    Abstract: Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 17, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Milind S. Bhagavat, Rahul Agarwal
  • Patent number: 10580964
    Abstract: The present invention relates to a memory device including a substrate and a lower electrode, buffer layer, seed layer, Magnetic Tunnel Junction (MTJ), capping layer, synthetic antiferromagnetic layer, and upper electrode formed on the substrate.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: March 3, 2020
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jea Gun Park, Du Yeong Lee, Song Hwa Hong, Jin Young Choi, Seung Eun Lee, Junli Li
  • Patent number: 10580969
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a first magnetic layer; a second magnetic layer; and a spacer layer interposed between the first magnetic layer and the second magnetic layer, wherein the spacer layer includes a first layer, a second layer and an intermediate layer interposed between the first layer and the second layer, and wherein each of the first layer and the second layer includes an oxide, or a nitride, or a combination of an oxide and a nitride, the intermediate layer includes a multilayer structure including [Ru/x]n or [x/Ru]n, x includes a metal, an oxide, or a nitride, or a combination of a metal, an oxide and a nitride, and n represents an integer of 1 or greater.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 3, 2020
    Assignees: SK hynix Inc., Toshiba Memory Corporation
    Inventors: Tae-Young Lee, Jae-Hyoung Lee, Sung-Woong Chung, Eiji Kitagawa
  • Patent number: 10580931
    Abstract: A method of manufacturing a gallium nitride light-emitting diode, including the successive steps of: a) forming a planar active gallium nitride light-emitting diode stack including first and second doped gallium nitride layers of opposite conductivity types and, between the first and second gallium nitride layers, an emissive layer with one or a plurality of quantum wells; and b) growing nanowires on the surface of the first gallium nitride layer opposite to the emissive layer.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: March 3, 2020
    Assignee: Commissariat √† l'√Čnergie Atomique et aux √Čnergies Alternatives
    Inventors: Ivan-Christophe Robin, Matthew Charles, Yohan Desieres
  • Patent number: 10566531
    Abstract: An illustrative method of fabricating a memory array structure includes: forming at least one access device layer on an upper surface of a first conductive layer, the access device layer being in electrical connection with the first conductive layer; forming a sacrificial layer on an upper surface of the access device layer; etching the access device layer and the sacrificial layer using a same masking feature to form an access device that is self-aligned with a portion of the sacrificial layer; replacing a portion of the sacrificial layer with memory storage material to form a storage element, a first terminal of the storage element being in electrical connection with the access device; and forming a second conductive layer on an upper surface of the storage element, a second terminal of the storage element being in electrical connection with the second conductive layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventor: Matthew J. BrightSky
  • Patent number: 10566500
    Abstract: An optoelectronic semiconductor component has a semiconductor body, wherein the semiconductor body includes a semiconductor layer sequence having a first semiconductor layer, a second semiconductor layer and an active region that generates or receives radiation disposed between the first semiconductor layer and the second semiconductor layer; the semiconductor body has a functional region in which the first semiconductor layer electrically conductively connects to a first terminal layer and the second semiconductor layer electrically conductively connects to a second terminal layer; an isolating layer is arranged on a side of the first terminal layer facing away from the semiconductor body; an interruption is formed in the isolating layer which at least locally delimits an inner subregion of the isolating layer in a lateral direction; the interruption encloses the functional region in the lateral direction; and in a plan view of the semiconductor component, the interruption overlaps with the active region.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: February 18, 2020
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Alexander F. Pfeuffer
  • Patent number: 10547016
    Abstract: A photoelectric conversion apparatus according to an embodiment includes a semiconductor substrate, a first electrode layer disposed on the semiconductor substrate, a second electrode layer disposed between the first electrode layer and the semiconductor substrate, an accumulation layer disposed between the first electrode layer and the second electrode layer and configured to accumulate signal electric charges generated by photoelectric conversion, an insulating layer disposed between the accumulation layer and the second electrode layer, a blocking layer disposed between the accumulation layer and the insulating layer and configured to prevent the signal electric charges in the accumulation layer from reaching the insulating layer, and a circuit unit disposed in the semiconductor substrate and connected to the second electrode layer to receive a signal based on the signal electric charges.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: January 28, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Kazuaki Tashiro
  • Patent number: 10546981
    Abstract: A light emitting device includes: a light emitting element emitting first light; a fluorescent material layer disposed on the light emitting element and excited by the first light to emit second light being longer in wavelength than the first light; a reflective film disposed on the fluorescent material layer to reflect the first light and transmit the second light; a light-transmissive member disposed on the reflective film; and an absorbing layer disposed on the light-transmissive member to absorb the first light.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 28, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Taiki Yuasa
  • Patent number: 10541348
    Abstract: A method comprising: depositing a quantum dot solution onto an as-grown layer of channel material to form a layer of quantum dot material having a substantially uniform thickness across the area of the layer of quantum dot material; and transferring the layers of channel and quantum dot material as a single stack onto a substrate comprising source and drain electrodes such that both the layers of channel and quantum dot material substantially conform to the topography of the underlying substrate and electrodes whilst maintaining the substantially uniform thickness of quantum dot material, the source and drain electrodes configured to enable a flow of electrical current through the layer of channel material, the layer of quantum dot material configured to generate electron-hole pairs on exposure to incident electromagnetic radiation to produce a detectable change in the flow of electrical current which is indicative of one or more of the presence and magnitude of the incident electromagnetic radiation.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 21, 2020
    Assignee: LYTEN, INC.
    Inventor: Richard White
  • Patent number: 10535720
    Abstract: Disclosed herein is an organic light emitting diode (OLED) lighting device capable of expressing characters or drawings with various colors. The OLED lighting device according to aspects of the present disclosure includes a thermochromic pattern arranged inside or outside of a substrate, the thermo chromic pattern having a property of changing a color thereof according to a change in temperature. By applying a reversible thermochromic pattern, which may maintain or lose an original color thereof according to a temperature change, to the inside or outside of the substrate, it is possible to express characters and drawings with various colors without designing a processing pattern inside the substrate.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: January 14, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Jungeun Lee