Abstract: An AMOLED display device and an array substrate thereof are disclosed. The array substrate of the AMOLED display device includes a baseplate, a surface-shaped power line, a point-shaped power line, and a plurality of insulating layers arranged between the surface-shaped power line and the point-shaped power line. The surface-shaped power line and the point-shaped power line are configured to provide a positive polarity power source to a light-emitting diode. The surface-shaped power line is formed on the baseplate, and the point-shaped power line is formed on the plurality of insulating layers. The surface-shaped power line and the point-shaped power line are electrically connected to each other through a via hole.

Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a display device. The manufacturing method of the thin film transistor includes: providing a substrate; depositing an active layer film, a gate insulator layer film, and a gate metal layer film on the substrate in sequence, patterning the active layer film, the gate insulator layer film, and the gate metal layer film to form an active layer, a gate insulator layer and a gate metal layer respectively, and depositing an insulator layer film at a first temperature and patterning the insulator layer film to form an insulator layer; a portion of the active layer, which portion is not overlapped with the gate metal layer, is treated to become conductive to provide a conductor during deposition of the insulator layer film.

Abstract: In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n++-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.

Abstract: Systems for LED illumination products. Solutions to the problems attendant to delivering a white-appearing LED product without diminishing efficiency of white light generation are presented. Devices are designed and manufactured that include a specially-formulated off-state white-appearing layer to the LED apparatus. The composition of the specially-formulated off-state white-appearing layer is tuned for high-efficiency during the on-state.

Abstract: A micro LED display panel includes a plurality of active areas disposed on a substrate and arranged in an array. A plurality of micro LEDs are uniformly arranged in each of the active areas to achieve high-resolution of micro LED display panel. By controlling the number of micro LEDs in each of the active areas, the production cost can be effectively controlled, while a screen door effect can be eliminated to thereby enhance market competitiveness of the micro LED display panel.

Abstract: An optoelectronic device including a semiconductor substrate having a face, light-emitting diodes arranged on the face and including wired conical or frustoconical semiconductor elements, and an at least partially transparent dielectric layer covering the light-emitting diodes, the refractive index of the dielectric layer being between 1.6 et 1.8.

Abstract: A method to fill the flowable material into the semiconductor assembly module gap regions is described. In an embodiment, multiple semiconductor units are formed on the substrate to create an array module; the array module is attached to a backplane having circuitry to form the semiconductor assembly module in which multiple gap regions are formed inside the semiconductor assembly module and edge gap regions are formed surround an edge of the assembly module; The flowable material is forced inside the gap regions by performing the high acting pressure environment and then cured to be a stable solid to form a robustness structure. A semiconductor convert module is formed by removing the substrate utilizing a substrate removal process. A semiconductor driving module is formed by utilizing a connecting layer on the semiconductor convert module. In one embodiment, a vertical light emitting diode semiconductor driving module is formed to light up the vertical LED array.

Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by providing a dual bottom spacer structure on physically exposed surfaces of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the dual bottom spacer structure prevents bottom up growth of the semiconductor material that provides the S/D regions.

Abstract: The present disclosure provides a semiconductor pattern and a method for preparing the same. The semiconductor pattern includes a substrate, a plurality of first semiconductor structures disposed over the substrate, a plurality of second semiconductor structures disposed over the substrate, and a semiconductor frame structure disposed over the substrate. The first semiconductor structures and the second semiconductor structures are alternately arranged. The semiconductor frame structure encircles the first semiconductor structures and the second semiconductor structures. The first semiconductor structures include a first length, the second semiconductor structures include a second length, and the first length of the first semiconductor structures is less than the second length of the second semiconductor structures.

Abstract: A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation; a gate positioned around the stacked n-channel device and p-channel device; and at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device. Each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted.

Abstract: Embodiments of the invention include a wavelength-converting material defined by AE3?x1?y+zRE3?x2+y?z[Si9?wAlw(N1?yCy)[4](N16?z?wOz+w)[2]]:Eux1,Cex2, where AE=Ca, Sr, Ba; RE=Y, Lu, La, Sc; 0?x1?0.18; 0?x2?0.2; x1+x2>0; 0?y?1; 0?z?3; 0?w?3.

Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

Abstract: A thin film transistor (TFT) device is provided with a glass substrate, a gate metal formed on a surface of the glass substrate; a gate insulating layer formed on the surface of the glass substrate, and covering the gate metal; an indium gallium zinc oxide (IGZO) layer formed on a surface of the gate insulating layer; a source metal and a drain metal formed on a surface of the IGZO layer, and a channel area is formed between the source metal and the drain metal; and a diffraction metal formed on the surface of the IGZO layer and located within the channel area.

Abstract: We disclose a high voltage semiconductor device comprising a semiconductor substrate of a second conductivity type; a semiconductor drift region of the second conductivity type disposed over the semiconductor substrate, the semiconductor substrate region having higher doping concentration than the drift region; a semiconductor region of a first conductivity type, opposite to the second conductivity type, formed on the surface of the device and within the semiconductor drift region, the semiconductor region having higher doping concentration than the drift region; and a lateral extension of the first conductivity type extending laterally from the semiconductor region into the drift region, the lateral extension being spaced from a surface of the device.

Abstract: A compound semiconductor device includes a substrate, including a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface includes a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein a convex region or a concave region is formed by the first deteriorated surface, the first crack surface and the second crack surface, or the second deteriorated surface, the first crack surface and the third crack surface; and wherein the second crack surface or the third crack surface is substantially perpendicular to the top surface or the bottom surface.

Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.

Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.

Abstract: Provided is a display device including first to third pixels and first to fourth cap layers. The first cap layer is located over and overlaps with the first to third light-emitting elements and extends from the first pixel to the third pixel through the second pixel. The second and third cap layers are located over the first cap layer and respectively overlap with the second and third light-emitting elements. The fourth cap layer is located over the first to fourth cap layers. The first to third pixels are arranged in this order. The first to third light-emitting elements are configured so that an emission wavelength of the second light-emitting element is shorter than an emission wavelength of the third light-emitting element and longer than an emission wavelength of the first light-emitting element. A thickness of the third cap layer is larger than a thickness of the second cap layer.

Abstract: A display panel and a display device are provided. The display panel comprises a first substrate having a step area; a second substrate disposed opposite to the first substrate, wherein the second substrate has a first surface facing the first substrate and an opposite second surface; a Chip On Flex (COF) disposed on the step area of the first substrate and comprising at least one ground pad, wherein the COF has a first surface facing the first substrate and an opposite second surface, and the at least one ground pad is disposed on the second surface of the COF; a conductive layer disposed on the second surface of the second substrate; and a conductive adhesive electrically connected to the conductive layer and the at least one ground pad.

Abstract: In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.