Abstract: An electroluminescence display device includes a pixel electrode; a first organic layer provided on the pixel electrode; a light emitting layer provided on the first organic layer; a second organic layer provided on the light emitting layer; and a counter electrode provided on the second organic layer. The light emitting layer includes a host material, a light emitting dopant material and an assist dopant material. The light emitting dopant material has a first concentration distribution in a thickness direction of the light emitting layer; the assist dopant material has a second concentration distribution in the thickness direction of the light emitting layer; and the first concentration distribution has a concentration peak in a range of the second concentration distribution.

Abstract: A structure comprises a first channel region forming an n-channel device; a second channel region forming a p-channel device, the p-channel device being stacked with the n-channel device in a vertical orientation; a gate positioned around the stacked n-channel device and p-channel device; and at least one source region and at least one drain region extending from each of the n-channel device and the p-channel device. Each of the at least one source region and the at least one drain region within the stacked n-channel device and p-channel device are independently contacted.

Abstract: A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and forming a plurality of trenches in the second surface of the substrate. The method also includes forming a semiconductor pillar in each of the plurality of trenches, wherein the semiconductor pillars and the substrate form a plurality of super junctions of the power semiconductor device for increasing the breakdown voltage of the power semiconductor device and reducing the on-stage voltage of the power semiconductor device; and forming a gate structure on the first surface of the substrate. Further, the method includes forming a plurality of well regions in the first surface of the substrate around the gate structure; and forming a source region in each of the plurality of well regions around the gate structure.

Abstract: A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.

Abstract: A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

Abstract: Embodiments are related to scalable surface structure (e.g., a well or other structure) formation in a substrate and, more particularly, to systems and methods for forming displays using a photo-machinable material layer.

Abstract: An optoelectronic device including a semiconductor substrate having a face, light-emitting diodes arranged on the face and including wired conical or frustoconical semiconductor elements, and an at least partially transparent dielectric layer covering the light-emitting diodes, the refractive index of the dielectric layer being between 1.6 et 1.8.

Abstract: A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

Abstract: The present invention provides an OLED display and a manufacturing method thereof. The OLED display of the present invention includes an OLED substrate and a thin film encapsulation layer disposed on the OLED substrate.

Abstract: A semiconductor device including a substrate, a gate stack, a pair of insulator structures, and source/drain materials is provided. The substrate has a plurality of recesses, wherein the plurality of recesses defines a protruded portion of the substrate having a channel region, and the protruded portion has a first side surface and a second side surface opposite to the first side surface. The gate stack is disposed on the protruded portion of the substrate. The pair of insulator structures are disposed within the plurality of recesses and respectively covering parts of the first side surface and the second side surface of the protruded portion, wherein the channel region is uncovered by the pair of insulator structures. The source/drain materials are disposed on the substrate in the plurality of recesses and on two opposing sides of the channel region, wherein the source/drain materials cover the pair of insulator structures.

Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of a wide bandgap semiconductor and a Schottky electrode formed to come into contact with a surface of the semiconductor layer, and has a threshold voltage Vth of 0.3 V to 0.7 V and a leakage current Jr of 1×10?9 A/cm2 to 1×10?4 A/cm2 in a rated voltage VR.

Abstract: Phased-array antenna systems can be constructed using transfer printed active components. Phased-array antenna systems benefit from a large number of radiating elements (e.g., more radiating elements can form sharper, narrower beams (higher gain)). As the number of radiating elements increases, the size of the part and the cost of assembly increases. High throughput micro assembly (e.g. by micro-transfer printing) mitigates costs associated with high part-count. Micro assembly is advantaged over monolithic approaches that form multiple radiating elements on a semiconductor wafer because micro assembly uses less semiconductor material to provide the active components that are necessary for the array. The density of active components on the phased-array antenna system is small. Micro assembly provides a way to efficiently use semiconductor material on a phased array, reducing the amount of non-active semiconductor area (e.g.

Abstract: A method of forming a semiconductor device includes receiving a structure having a substrate, a gate trench over the substrate, and a dielectric layer over the substrate and surrounding the gate trench. The method further includes forming a gate dielectric layer in the gate trench, forming a barrier layer in the gate trench and over the gate dielectric layer, and treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer. The method further includes forming an n-type work function metal layer over the treated barrier layer.

Abstract: A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric layer. The doped dielectric layer includes a first doped layer and a second doped layer. The passivation structure further includes a top dielectric layer over the doped dielectric layer.

Abstract: The present invention provides an OLED display and a manufacturing method thereof. The OLED display of the present invention is such that in a thin film encapsulation layer, an inorganic passivation that is located under and adjacent to each organic buffer layer forms a stepped zone at a portion between an outer edge of the organic buffer layer and an outer edge of the inorganic passivation layer and each stepped zone is provided with a DLC layer that covers the stepped zone. In other words, the present invention uses DLC for later side encapsulation and in the thin film encapsulation layer, each organic buffer layer is provided, on an outer side thereof, with a DLC layer to thereby effectively block external moisture and oxygen from attacking the OLED device from a lateral side and also to eliminate an issue of loss for light of a top emission device to travel through DLC.

Abstract: A semiconductor structure includes a substrate including a plurality of vias passing through the substrate and filled with a conductive or semiconductive material, and an oxide layer surrounding the conductive or semiconductive material, the substrate defining a cavity therein; a membrane disposed over the substrate and the cavity; a heater disposed within the membrane and electrically connected with the substrate; and a sensing electrode disposed over the membrane and the heater.

Abstract: In an active region, a contact trench in which a source electrode is embedded is provided. In a boundary region between the active region and the edge termination region, a tapered trench is provided. A second p-type base region is provided along an inner wall of the contact trench and extends to the boundary region to be provided along a base front surface and an inner wall of the tapered trench. An angle ?3 of the side walls of the tapered trench with respect to a substrate front surface is smaller than an angle ?1 of the side walls of the contact trench with respect to the substrate front surface. At a second mesa portion between the tapered trench and a step of the edge termination region, a gate runner is arranged on the base front surface, via a field oxide film.

Abstract: A light-emitting diode (LED) projector includes an LED display panel and a projection lens arranged in front of LED display panel and configured to collect and project light emitted by the LED display panel. The LED display panel includes an LED panel and a micro lens array arranged over the LED panel. The LED panel includes a substrate, a driver circuit array on the substrate and including a plurality of pixel driver circuits arranged in an array, and an LED array including a plurality of LED dies each being coupled to one of the pixel driver circuits. The micro lens array includes a plurality of micro lenses each corresponding to and being arranged over at least one of the LED dies.

Abstract: A semiconductor device includes a first diode having a cathode connected to a first terminal, a second diode having a cathode connected to a second terminal and an anode connected to an anode of the first diode, a third diode having an anode connected to the first terminal and the cathode of the first diode, a fourth diode having an anode connected to the second terminal and the anode of the second diode and a cathode connected to a cathode of the third diode, and a fifth diode having an anode connected to the anode of the first diode and the anode of the second diode and a cathode connected to the cathode of the third diode and the fourth diode. A breakdown voltage of the fifth diode is lower than the breakdown voltages of the first diode, the second diode, the third diode, and the fourth diode.

Abstract: A light emitting device can include a GaN layer having a multilayer structure that can include an n-type layer, an active layer, and a p-type layer, the GaN layer having a first surface and a second surface; a conductive structure on the first surface of the GaN layer, the conductive structure includes a first electrode in contact with the first surface of the GaN layer, the first electrode is configured to reflect light from the active layer back through the second surface of the GaN layer; and a metal layer including Au, in which the metal layer serves as a first pad; a second electrode on the second surface of the GaN layer; and a second pad on the second electrode, in which a thickness of the second pad is about 0.5 ?m or higher.