Abstract: A method and device for data storage are provided. The method includes determining, based on a write message corresponding to a first file, an application corresponding to the first file, a file type of the first file, and first attribute information corresponding to the file type, the first attribute information corresponding to the file type obtained based on second attribute information corresponding to all files of the file type on which the write operation processing have been performed in response to the respective write messages of the application, predicting a stream identification information corresponding to the first file by using a file classifier based on the application corresponding to the first file, the file type of the first file and the first attribute information corresponding to the file type, and sending a writing command carrying the stream identification information to a storage device.

Abstract: Reliability in a storage system can be easily and appropriately improved. In a computer system including a storage system configured to provide a plurality of instances in any one of a plurality of subzones divided by risk boundaries, a processor of the computer system is configured to make a storage controller that controls I/O processing for a volume based on a capacity pool provided by a plurality of storages redundant to the plurality of instances provided in the plurality of subzones.

Abstract: A control circuit for a non-volatile memory array includes an interface to receive requests, a common request queue connected to the interface and a common request buffer connected to the common request queue. The common request buffer is configured to receive the requests from the common request queue in their received order and buffer unfinished requests directed to memory addresses such that for any address in the non-volatile memory array no more than one unfinished request is in the common request buffer.

Abstract: A method used in a flash memory controller includes: using an error correction code (ECC) circuit to perform an ECC operation upon data of a block of a flash memory chip/die of a flash memory device to generate an ECC result; when the ECC result indicates a failure, storing an access task corresponding to the block into a specific buffer; and, controlling a voltage generator of the flash memory device through a specific communication interface to control at least one address decoder of the flash memory device to access the block of the flash memory chip/die again according to at least one threshold voltage level of the voltage generator after the access task has been temporarily stored in the specific buffer for a specific default time.

Abstract: A technique for managing transient snapshots identifies an instruction to create a transient snapshot with an indicator and attempts to delay, based on the indicator, flushing of the instruction from cache to a mapping subsystem at least until the cache receives an instruction to delete the transient snapshot.

Abstract: To provide a data sharing system and a data sharing method that make it easy to suppress the disclosure of data whose disclosure is restricted according to the location where the data exists, in accordance with the provision of the disclosure restriction. A data sharing system comprising a storage node having virtual volumes accessed by a readout device, the data sharing system comprising: the storage node comprises: an access setting unit configured to restrict a target readout device from reading data from a target virtual volume in accordance with information on a location of the target readout device accessing the data sharing system and information on a location of the target virtual volume from which the target readout device attempts to read data.

Abstract: A method of operating a non-volatile memory device is provided. The device includes a latch, a page buffer and blocks, each of which includes pages. The method includes: receiving a page command for a write operation corresponding to a page of one of the blocks; receiving a write command for writing data to the page buffer; latching preexisting latched data or random data generated as latched data; writing the latched data to a page of a new block from among the plurality of blocks that corresponds to a page address based on the write command; and repeatedly updating the page address and repeatedly writing the latched data to additional pages corresponding to each updated page address until each page of the new block has been written to.

Abstract: An apparatus in one embodiment comprises at least one processing device configured to detect a plurality of asynchronous events in a storage system, wherein the storage system is configured to provide respective individual asynchronous event notifications for the detected asynchronous events to a host device in response to receipt of corresponding asynchronous event requests from the host device. The at least one processing device is further configured to determine that multiple ones of the asynchronous events have been detected in the storage system without receipt of respective ones of the corresponding asynchronous event requests from the host device, and to provide to the host device in response to a particular one of the asynchronous event requests received from the host device a summary notification comprising information indicative of the multiple detected asynchronous events. The at least one processing device illustratively comprises at least one storage controller of the storage system.

Abstract: The present disclosure relates to establishing a tightly coupled integration between a decentralized blockchain network and a centralized storage array. In embodiments, a first set of storage operations on a snapshot of a storage array are performed. Further, data blocks generated from the snapshot are broadcast to at least one computing network for the at least one computing network's nodes to perform a second set of storage operations.

Abstract: The present disclosure provides storage nodes, integrated circuits, and methods for storage node management. A method for storage node management includes performing one or more network tasks by one or more first processing cores in a network engine of an integrated circuit; and performing one or more storage tasks by one or more second processing cores in a storage engine of the integrated circuit.

Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

Abstract: A memory device includes sets of memory dies. Each set of memory dies includes a memory dies associated with a respective channel of a plurality of channels, and each channel of the plurality of channels has a respective ready busy (RB) signal. The memory device further includes an input/output (I/O) expander to perform operations including receiving at least one command to perform clock synchronization associated with a clock signal with respect to the plurality of sets of memory dies, and in response to receiving the command, causing circuitry of the I/O expander to be configured to create an RB signal short with respect to a particular combination of channels. The clock synchronization is associated with peak power management (PPM) initialization.

Abstract: A compression-expansion control apparatus has a reconfiguration portion capable of configuring one or more compression circuits which compress data in plain text and/or one or more expansion circuits which expand the compressed data on a programmable logical circuit component, a waiting-time observing portion which observes processing waiting-time from when compression processing was requested till when the compression processing is started and processing waiting-time from when expansion processing was requested till when the expansion processing is started, a calculating portion which determines the number or a ratio of the compression circuits and the expansion circuits in the reconfiguration portion on the basis of the processing waiting-time of the compression processing and the processing waiting-time of the expansion processing, and a switching portion which executes reconfiguration of the compression circuit and/or the expansion circuit in the reconfiguration portion on the basis of the number or the r

Abstract: The present disclosure is directed to a novel reconfiguration framework for a BFT SMR system. With this framework, the configuration of both the system itself and the clients of the system can be modified in a live manner (i.e., without taking the system offline) while preserving correct system operation.

Abstract: An apparatus comprises processing circuitry to issue store operations to store data to a data store and load operations to load data from the data store and a store buffer comprising entries to store entry information corresponding to store operations in advance of the store operations completing. Store buffer lookup circuitry is provided to lookup, in response to a load operation, whether the store buffer contains a corresponding entry corresponding to an older store operation for which target addresses of the load operation and the older store operation satisfy an address comparison condition. The store buffer lookup circuitry is configured to perform store-to-load forwarding in response to the load operation when the corresponding entry is a first type of store buffer entry satisfying a forwarding condition, and delay processing of the load operation when the corresponding entry is a second type of store buffer entry satisfying the forwarding condition.

Abstract: The present disclosure provides storage devices and methods for operating the same. In some embodiments, a storage device includes a non-volatile memory including a plurality of sub-blocks that are independently erasable, and a processor configured to control a garbage collection operation on the plurality of sub-blocks. The plurality of sub-blocks includes a plurality of first sub-blocks that have a first block size and a plurality of second sub-blocks that have a second block size. The second block size is different from the first block size. The processor is further configured to select a victim sub-block with a lowest ratio of a valid page count to an invalid page count from among the plurality of sub-blocks, and copy a valid page of the victim sub-block to a target sub-block from among the plurality of sub-blocks.

Abstract: Logical address slices and corresponding metadata pages of mapping information can be partitioned into sets. Each node can be assigned exclusive ownership of one of the sets. In at least one embodiment, for a read I/O which is received at a first node and directed to a logical address LA1 that is owned by a second node, the first node can request that the second owning node perform resolution processing for LA1. The second node can own both LA1 and corresponding metadata pages included in mapping information used to map LA1 to a corresponding physical location PA1 including content C1 stored at LA1. The second node can perform resolution processing for LA1 using the metadata pages corresponding to LA1 to either read and return C1 to the first node, or obtain and return PA1 to the first node where the first node can then read C1 directly using PA1.

Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

Abstract: A memory system includes a first semiconductor memory device, a second semiconductor memory device, and a controller for controlling operations thereof. Each of the first and second semiconductor memory devices includes a normal area and a preliminary area. The controller is configured to determine a data migration operation on target data stored in the first semiconductor memory device and in response thereto control the first semiconductor memory device to read the target data, generate migration data including a plurality of group migration complete data indicating that the data migration operation has been partially completed based on the target data, and control the second semiconductor memory device to program the migration data in the preliminary area of the second semiconductor memory device.

Abstract: Dual-controller storage systems and methods for controlling the dual-controller storage systems are provided. The dual-controller storage system may include a first controller, a second controller, at least one expander, a first storage array, and a second storage array. The at least one expander may be connected with the first controller, the second controller, the first storage array, and the second storage array. The first controller and the second controller may be communicatively connected via a network. When the first controller and the second controller both work in a normal state, the first controller may be configured to control the first storage array, and the second controller may be configured to control the second storage array. The first controller and the second controller may work in synchronization.