Patents Examined by Mohamed M Gebril
  • Patent number: 10691614
    Abstract: Techniques to manage virtual memory are disclosed. In various embodiments, a time domain page access signal of a page is transformed to a frequency domain to obtain an access frequency. The access frequency is used to manage storage of the page in a page cache in memory. The access frequency may be used to evict the page from the page cache or, in some embodiments, to predictively load the page into the page cache.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: June 23, 2020
    Assignee: TIBCO SOFTWARE INC.
    Inventor: Suresh Subramani
  • Patent number: 10684923
    Abstract: A real time file alteration sensing-based automatic backup device includes: a backup target selection unit selecting one or more backup targets that are accessible over a network and are subjected to backup; a content alteration sensing unit sensing in real time whether contents of the one or more backup targets are altered or scanning all the backup targets for sensing at particular-time intervals; a backup data generation unit generating, when the alteration of the content of the backup target is sensed, backup data containing information required for recovery of the sensed backup target; and a backup data storage unit storing the generated backup data.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: June 16, 2020
    Inventor: Ho Jun Lee
  • Patent number: 10656866
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device selects storage parameters for a multi-vault synchronization process from a first storage vault to a second storage vault. The computing device synchronizes storage of the set(s) of ingestion encoded data slices (EDSs) between the vaults and maintains storage of a portion of an ingestion data stream within the second storage vault. The computing device facilitates deletion of the set(s) of ingestion EDSs corresponding to the portion of an ingestion data stream from the first storage vault. the computing device performs additional multi-vault synchronization process(es) for any other portion(s) of the ingestion data stream.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 19, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Adam M. Gray, Greg R. Dhuse, Andrew D. Baptist, Ravi V. Khadiwala, Wesley B. Leggette, Scott M. Horan, Franco V. Borich, Bart R. Cilfone, Daniel J. Scholl, Kumar Abhijeet, Praveen Viraraghavan
  • Patent number: 10649670
    Abstract: Embodiments of the present disclosure relates to data block processing in a distributed processing system. According to one embodiment of the present disclosure, a computer-implemented method is proposed. A first performance indicator for processing a data block by a first processing module is obtained, where the data block is loaded into the first processing module. Then, a second performance indicator for processing the data block by a second processing module is obtained, where the first and second processing modules being logical instances launched in a distributed processing system for processing data blocks. Next, one processing module is selected from the first and second processing modules for processing the data block based on a relationship between the first and second performance indicators.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Liang Liu, Junmei Qu, Hong Zhou Sha, Wei Zhuang
  • Patent number: 10649672
    Abstract: A set of device maintenance related data is received from each of a plurality of non-volatile memory modules. Each of the plurality of non-volatile memory modules comprise a plurality of non-volatile memory devices. Based at least in part on said set of device maintenance related data a maintenance operation to be performed is determined. The determined device maintenance related operation is performed.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 12, 2020
    Assignee: EMC IP Holding Company LLC
    Inventor: Michael Nishimoto
  • Patent number: 10643700
    Abstract: According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shekoufeh Qawami, Rajesh Sundaram
  • Patent number: 10635602
    Abstract: Address translation of a base address prior to receiving a storage reference to use the address. A determination is made that an address has been obtained that is to be used as a base address for a memory location at which one or more in-memory configuration state registers are stored. Based on the determining, the address is translated into another address, and the translating is performed prior to receiving a storage reference to use the base address.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10620869
    Abstract: A storage control device according to the present invention connected to a master disk device that stores data into a plurality of segments continuously, and a plurality of copy disk devices that are copy destinations of the data, the storage control device includes: a clone processing unit that, when receiving a copy instruction for one of the copy disk devices, repeats reading and writing of each of the segments in order of address to complete copy, and that, when a first copy disk that is the copy disk device other than a later copy disk that is the specified copy disk device is during copy when receiving the copy instruction, starts copy of the later copy disk from the segment during reading, and, after the completion of reading data of the segment, performs writing into both the first copy disk and the later copy disk.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: April 14, 2020
    Assignee: NEC CORPORATION
    Inventor: Toshitaka Nakashima
  • Patent number: 10613768
    Abstract: A checkpointing module, a method for storing checkpoints and a microserver including a checkpointing module for storing checkpoints are proposed. The checkpointing module includes an interconnect interface configured to receive checkpoints from at least one compute module, one or more non-volatile random access memory devices configured to store the received checkpoints, a memory management entity configured to assign storage locations for the received checkpoints in the one or more non-volatile random access memory devices, and a memory controller configured to store the received checkpoints at the assigned storage locations.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventor: Andreas Christian Doering
  • Patent number: 10606510
    Abstract: A system for managing memory input/output management is provided herein. The system may include a processor and a memory storing machine-readable instructions that when executed by the processor, cause the system to perform operations including receiving read requests for first data stored on a solid-state storage drive, receiving write requests for second data to be stored on the storage drive, placing at least some of the read requests in a first queue, placing at least some of the write requests in a second queue, the second queue having a size limit, processing data at a disk driver layer from the first queue and the second queue in a manner such that selection of a request from either queue is biased towards the first queue. Associated methods are also included.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 31, 2020
    Assignee: Netflix, Inc.
    Inventor: M. Warner Losh
  • Patent number: 10606514
    Abstract: In a control program for one storage control device in a storage device that includes a plurality of storage control devices that control storages and in which configuration information related to configurations of the storages is synchronized among the storage control devices, a process includes; storing, when having received a command to change the configuration information while another storage control device is executing update processing of updating a firmware, specification information specifying a plurality of divided pieces of command processing obtained by dividing processing of the command into executable units in a storage region; and executing each of the divided pieces of the command processing specified by the specification information while the other storage control device is executing any divided piece of the update processing, executable in parallel with the processing of the command.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: March 31, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Masahiro Yoshida, Tomohiko Muroyama
  • Patent number: 10599576
    Abstract: Techniques that facilitate hybrid memory access frequency are provided. In one example, a system stores access frequency data for storage class memory and volatile memory in a translation lookaside buffer. The access frequency data is indicative of a frequency of access to the storage class memory and the volatile memory. The system also determines whether to store data in the storage class memory or the volatile memory based on the access frequency data stored in the translation lookaside buffer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hubertus Franke, Bulent Abali, Damir Anthony Jamsek, Marcio Augusto Silva
  • Patent number: 10592421
    Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Carlos V. Rozas, Ilya Alexandrovich, Ittai Anati, Alex Berenzon, Michael A. Goldsmith, Barry E. Huntley, Anton Ivanov, Simon P. Johnson, Rebekah M. Leslie-Hurd, Francis X. McKeen, Gilbert Neiger, Rinat Rappoport, Scott D. Rodgers, Uday R. Savagaonkar, Vincent R. Scarlata, Vedvyas Shanbhogue, Wesley H. Smith, William C. Wood
  • Patent number: 10579264
    Abstract: A memory system may include: a plurality of memory dies; and a controller suitable for identifying a dependency between first and second commands and a priority order of the first and the second commands through a check engine, and control the memory dies to sequentially perform first and second command operations in response to the first and second commands according to the dependency and the priority order.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong-Sop Lee
  • Patent number: 10565127
    Abstract: An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Yao Zu Dong, Kun Tian
  • Patent number: 10552070
    Abstract: Grouping of memory-based configuration state registers based on execution environment. A first set of configuration state registers is assigned to one memory region corresponding to a first execution environment, and a second set of configuration state registers is assigned to another memory region corresponding to a second execution environment. The first set of configuration state registers is separate from the second set of configuration state registers.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10540275
    Abstract: To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: January 21, 2020
    Assignee: Sony Corporation
    Inventors: Hideaki Okubo, Kenichi Nakanishi, Yasushi Fujinami
  • Patent number: 10528519
    Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed is a cache coherency protocol that includes both an “Owned” state and a Forward state together with protocol mechanism for handling various memory requests.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: January 7, 2020
    Assignee: Mellanox Technologies Ltd.
    Inventor: Mark Rosenbluth
  • Patent number: 10515017
    Abstract: A computing system comprises at least one processing unit, at least one memory controller in communication with the processing unit, and a main memory in communication with the processing unit through the memory controller. A memory hierarchy of the computing system includes at least one cache, the memory controller, and the main memory. The memory hierarchy is divided into a plurality of memory pools. The main memory comprises a set of memory modules split in ranks each having a rank address defined by a set of rank address bits. Each rank has a set of memory devices comprising one or more banks each having a bank address defined by a set of bank address bits. A plurality of threads execute on the processing unit, and are assigned to the memory pools based on one or more memory partitioning techniques, including bank partitioning, rank partitioning, or memory controller partitioning.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 24, 2019
    Assignee: Honeywell International Inc.
    Inventors: Pavel Zaykov, Lucie Matusova
  • Patent number: 10515023
    Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, Gilbert Neiger, Vedvyas Shanbhogue, David M. Durham, Andrew V. Anderson, David A. Koufaty, Asit K. Mallick, Arumugam Thiyagarajah, Barry E. Huntley, Deepak K. Gupta, Michael Lemay, Joseph F. Cihula, Baiju V. Patel