Patents Examined by Mohamed M Gebril
  • Patent number: 11960761
    Abstract: A memory control method is disclosed according to an embodiment. The method includes: temporarily storing first type data into a buffer memory, wherein the first type data is preset to be stored into a rewritable non-volatile memory module based on a first programming mode; in a state that the first type data is stored in the buffer memory, temporarily storing second type data into the buffer memory, and the second type data is preset to be stored into the rewritable non-volatile memory module based on a second programming mode different from the first programming mode; and in a state that a data volume of the first type data in the buffer memory does not reach a first threshold, if a data volume of the second type data in the buffer memory reaches a second threshold, storing the first type data in the buffer memory into the rewritable non-volatile memory module.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chun-Yang Hu, Yi-Tein Hung
  • Patent number: 11954335
    Abstract: Reliability in a storage system can be easily and appropriately improved. In a computer system including a storage system configured to provide a plurality of instances in any one of a plurality of subzones divided by risk boundaries, a processor of the computer system is configured to make a storage controller that controls I/O processing for a volume based on a capacity pool provided by a plurality of storages redundant to the plurality of instances provided in the plurality of subzones.
    Type: Grant
    Filed: September 22, 2022
    Date of Patent: April 9, 2024
    Assignee: HITACHI, LTD.
    Inventors: Takaki Nakamura, Hideo Saito, Naruki Kurata, Takahiro Yamamoto
  • Patent number: 11941253
    Abstract: A method, computer program product, and computing system for sensing a failure within a system within a computing device. The system may include a cache memory system and a vaulted memory comprising a random access memory (RAM) having a plurality of independent persistent areas. A primary node and secondary node may be provided. The primary node may occupy a first independent persistent area of the RAM of the vaulted memory. The secondary node may occupy a second independent persistent area of the RAM of the vaulted memory. Data within the vaulted memory may be written to a persistent media using an iterator. The data may include at least one dirty page. Writing data within the vaulted memory to the persistent media may include flushing the at least one dirty page to the persistent media.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: March 26, 2024
    Assignee: EMC IP Holding Company, LLC
    Inventors: Oran Baruch, Ronen Gazit, Jenny Derzhavetz
  • Patent number: 11922059
    Abstract: A method of distributedly storing data in a system comprising a plurality of edge nodes communicatively coupled to an end device and a central cloud. The method includes: receiving, by a first edge node, data transmitted by the end device; assigning, by the first edge node, a data tag to received data according to attributes of the received data and duplicating the received data to generate a tagged data copy; and transmitting, by the first edge node, the tagged data copy to at least one second edge node determined by a data distribution policy determined by the central cloud directly or through the central cloud, so that the at least one second edge node store the tagged data copy in a storage.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 5, 2024
    Assignee: Penta Security Systems Inc.
    Inventors: Myung Woo Chung, Chel Park, Sang Gyoo Sim, Eui Seok Kim, Duk Soo Kim, Seok Woo Lee
  • Patent number: 11899937
    Abstract: Systems and methods of a memory allocation buffer to reduce heap fragmentation. In one embodiment, the memory allocation buffer structures a memory arena dedicated to a target region that is one of a plurality of regions in a server in a database cluster such as an HBase cluster. The memory area has a chunk size (e.g., 2 MB) and an offset pointer. Data objects in write requests targeted to the region are received and inserted to the memory arena at a location specified by the offset pointer. When the memory arena is filled, a new one is allocated. When a MemStore of the target region is flushed, the entire memory arenas for the target region are freed up. This reduces heap fragmentation that is responsible for long and/or frequent garbage collection pauses.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: February 13, 2024
    Assignee: Cloudera, Inc.
    Inventor: Todd Lipcon
  • Patent number: 11893281
    Abstract: A storage device includes a non-volatile memory (NVM) and a storage device controller. The storage device controller includes a NVM interface coupled to the NVM and one or more task queues. The storage device controller is operable to pick a task from one or more queues of the storage device. The task is parsed based upon presence of an extra header segment with an execution condition. The task without the extra header segment is sent to execution. Whether the execution condition of the extra header segment of the task is met is determined. The task with the execution condition met is sent to execution. The task with the execution condition unmet is postponed.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: February 6, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomer Spector, Doron Ganon, Eran Arad
  • Patent number: 11880579
    Abstract: A data migration method and a storage device are provided. The device obtains data access temperature of a first storage unit group, which is determined by data access temperature of each storage unit, and the data access temperature of each storage unit is determined by a logical unit in which the storage unit is located. When the data access temperature of the first storage unit group reaches a specified threshold, the storage device migrates data in the first storage unit group to a second storage unit group. Access performance of the second storage unit group is higher than access performance of the first storage unit group. According to this application, accuracy of collecting statistics about data access temperature can be improved, thereby improving hierarchical storage performance of a storage device.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: January 23, 2024
    Assignee: Huawei Technologies Co., Ltd.
    Inventor: Yu Lin
  • Patent number: 11868630
    Abstract: A storage system includes a first node mounting two controllers. The two controllers of the first node are subjected to setting of redundancy such that the two controllers belong to differing redundancy groups, respectively. When a configuration change is requested due to addition of a second node mounting one controller to the storage system, the second node sets the controller of the second node belongs to a redundancy group to which either of the two controllers of the first node belongs, and the first node changes the setting of redundancy such that setting information on the redundancy group of either of the two controllers of the first node does not change; and deactivates a controller of the first node for which the setting information on the redundancy group changes as a result of a change in the setting of redundancy.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: January 9, 2024
    Assignee: Hitachi, Ltd.
    Inventors: Jun Tsukioka, Yutaka Oshima
  • Patent number: 11868638
    Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sourabh Dhir, Kang-Yong Kim
  • Patent number: 11789652
    Abstract: A storage device includes a non-volatile memory; a plurality of cores; a host interface configured to receive a first set command, an I/O command, and an ADMIN command from a host; and a storage controller including a command distribution module configured to be set to a first state according to the first set command, and distribute the I/O command to the plurality of cores according to the set first state. Each of the plurality of cores may be configured to perform an operation instructed by the I/O command and an operation instructed by the ADMIN command on the non-volatile memory in response to the distributed I/O command.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum Hoe Koo, Jae Sub Kim, Yang Woo Roh, Dong Heon Ryu
  • Patent number: 11782637
    Abstract: Aspects and features of the present disclosure can prefetch metadata in the nodes of a cloud-based storage system. At a node that stores at least one shard of a data object, metadata for the data object can be fetched from node storage and saved in a node cache prior to processing a read request for the shard. The metadata can be cached in response to a prefetch request transmitted to the node, for example, by the gateway that shards data objects for the storage system. Thus, the metadata can be available in the node cache when the read request for the data shard arrives later, reducing delays in accessing data object shards from the storage nodes of the system.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: October 10, 2023
    Assignee: Red Hat, Inc.
    Inventors: Gabriel Zvi BenHanokh, Joshua Durgin
  • Patent number: 11768771
    Abstract: The techniques described herein improve cache traffic performance in the context of contended lock instructions. More specifically, each core maintains a lock address contention table that stores addresses corresponding to contended lock instructions. The lock address contention table also includes a state value that indicates progress through a series of states meant to track whether a load by the core in a spin-loop associated with semaphore acquisition has obtained the semaphore in an exclusive state. Upon detecting that a load in a spin-loop has obtained the semaphore in an exclusive state, the core responds to incoming requests for access to the semaphore with negative acknowledgments. This allows the core to maintain the semaphore cache line in an exclusive state, which allows it to acquire the semaphore faster and to avoid transmitting that cache line to other cores unnecessarily.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: September 26, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John M. King, Gregory W. Smaus
  • Patent number: 11762559
    Abstract: In one aspect of write sort management in accordance with the present disclosure, a write sort task related to write sorting a write list of data units to be destaged to storage, is assigned to a storage controller to improve the load balance among plural storage controllers. In one embodiment, available processing capacities of each of the storage controllers is determined by, for example, polling each of the storage controllers. A write sort task may then be assigned to a selected storage controller as a function of determined available processing capacities of each of the storage controllers to improve the load balance among the storage controllers. Other aspects and advantages are provided, depending upon the particular application.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: September 19, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian D. Hatfield, Lokesh Mohan Gupta, Matthew G. Borlick
  • Patent number: 11755229
    Abstract: Archival task processing in a data storage system is described herein. A method as described herein can include designating, by a device operatively coupled to a processor, a file stored by a primary cluster of a data storage system for archival to a remote storage system; locating, by the device, a secondary cluster of the data storage system having stored thereon a copy of the file, the secondary cluster being distinct from the primary cluster; and, in response to determining that the file stored by the primary cluster matches the copy of the file stored by the secondary cluster, causing, by the device, the secondary cluster to archive the copy of the file to the remote storage system.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: September 12, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Shiv Shankar Kumar, Avadut Mungre
  • Patent number: 11726663
    Abstract: Techniques for providing dependency resolution for lazy snapshots in a storage cluster with a delta log-based architecture. The techniques include creating a dependency relationship between a parent metadata page and a child metadata page, receiving one or more new delta updates of the parent metadata page, and writing, to a metadata delta log, the new delta updates of the parent metadata page as specialized delta update entries that preserve or maintain the new delta update values and their corresponding original (old) delta update values. By preserving or maintaining both the new delta update values and the corresponding old delta update values of the parent metadata page in the metadata delta log, constraints pertaining to the order of de-staging the delta updates of the parent and child metadata pages can be reduced.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: August 15, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Bar David, Michael Litvak
  • Patent number: 11709618
    Abstract: Methods, apparatus, and processor-readable storage media for automatically processing storage system data and generating visualizations representing differential data comparisons are provided herein. An example computer-implemented method includes obtaining current data from a first storage system and historical data from the first storage system and/or one or more additional storage systems; determining, for the first storage system, at least one current state value for at least one storage system parameter by processing the current data using a first hashing algorithm; determining, for the first storage system with respect to the first storage system and/or the additional storage systems, at least one differential state value for the at least one storage system parameter by processing the current data and the historical data using a second hashing algorithm; and generating data visualizations based on the current state value(s) and/or the differential state value(s).
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: July 25, 2023
    Assignee: Dell Products L.P.
    Inventors: Deepak Nagarajegowda, Bina K. Thakkar
  • Patent number: 11681628
    Abstract: A first cache of a first IOA is detected storing an amount of data that satisfies a memory shortage threshold. A request for extra memory for the first IOA is transmitted. The request is sent in response to detecting that the first cache stores the amount of data that satisfies the memory shortage threshold. The request is transmitted to a plurality of IOAs of a computer system. A second cache of a second IOA is detected storing an amount of data that satisfies a memory dissemination threshold. Memory of the second cache is allocated to the first cache. The memory is allocated in response to the request and the amount of data in the second cache satisfying the memory dissemination threshold.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 20, 2023
    Assignee: International Business Machines Corporation
    Inventors: Clark A. Anderson, Adrian C. Gerhard, William J. Maitland, Jr.
  • Patent number: 11681466
    Abstract: Example storage systems, storage devices, and methods provide proactive management of storage operations to, for example, beneficially minimize bottlenecking, latency, and other issues. An example system has a storage pool with a first storage device and a second storage device, and a processor configured to generate a storage request including a storage command, include a command processing time constraint in the storage request, send the storage request to the first storage device, and receive, from the first storage device, a proactive response including an estimation for an execution of the storage command by the first storage device based on the command processing time constraint. The processor may then select a fallback mechanism for executing the storage command based on the proactive response.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 20, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Patent number: 11656992
    Abstract: A programmable switch receives a cache line request from a client of a plurality of clients on a network to obtain a cache line. One or more additional cache lines are identified based on the received cache line request and prefetch information. The cache line and the one or more additional cache lines are requested from one or more memory devices on the network. The requested cache line and the one or more additional cache lines are received from the one or more memory devices, and are sent to the client.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 23, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marjan Radi, Dejan Vucinic
  • Patent number: 11650742
    Abstract: A computer system stores metadata that is used to identify physical memory devices that store randomly-accessible data for memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. Stored metadata associates a first address range of the address space with a first memory device, and a second address range of the address space with a second memory device. The operating system manages processes running on the computer system by accessing the stored metadata. This management includes allocating memory based on the stored metadata so that data for a first process is stored in the first memory device, and data for a second process is stored in the second memory device.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 16, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth Marion Curewitz, Shivasankar Gunasekaran, Ameen D. Akel, Hongyu Wang, Justin M. Eno, Shivam Swami, Samuel E. Bradshaw