Abstract: According to one embodiment, a storage device includes a first memory cell; a second memory cell; and a controller configured to, in response to receiving a first command set, execute a first erase operation which is included in an erase operation of data of the first memory cell, and suspend the first erase operation, and in response to receiving a second command set, execute a read operation or a write operation of the second memory cell and subsequently resume the suspended first erase operation.

Abstract: A storage system in one embodiment is configured to participate as a source storage system in a synchronous replication process with a target storage system. In verifying synchronously replicated data, the source storage system generates a current snapshot for one or more storage volumes subject to synchronous replication to the target storage system, identifies a plurality of pages of the current snapshot that have changed since generation of a previous snapshot for the one or more storage volumes, obtains content-based signatures for respective ones of the changed pages, assigns the changed pages to a page group, generates a group signature for the page group based at least in part on the content-based signatures of the pages of the page group, and sends the group signature to the target storage system. The group signature is configured to allow the target storage system to determine if the page group contains at least one page that is inconsistent between the source and target storage systems.

Abstract: One embodiment provides an apparatus. The apparatus includes first memory controller circuitry to control read and/or write access to first memory circuitry via a first conductive bus. The apparatus includes second memory controller circuitry to control read and/or write access to second memory circuitry via a second conductive bus. The apparatus includes power control circuitry coupled to the first memory controller circuitry and the second memory controller circuitry. The power control circuitry transfers data from the second memory circuitry with the second memory controller circuitry via the second conductive bus to the first memory circuitry with the first memory controller circuitry via the first conductive bus. The power control circuitry powers down the second memory circuitry after the transfer of the data from the second memory circuitry to the first memory circuitry. The power control circuitry decreases power consumption of the apparatus and may increase batter life of the apparatus.

Abstract: A method and an apparatus for data storage system are provided. The method comprises: receiving an I/O request from an upper layer, the I/O request including an I/O type identifier; determining an I/O type of the I/O request based on the I/O type identifier; and processing the I/O request based on the determined I/O type. The present disclosure also provides a corresponding apparatus. The method and the apparatus according to the present disclosure can determine a storage policy of corresponding data based on different I/O types to improve the overall system performance.

Abstract: An information processing system includes a first processor that issues a first write request group including a plurality of data write requests for writing first data to a memory. The first processor issues a first completion write request after issuing the first write request group. The first completion write request is a request for writing completion information to the memory. The completion information indicates completion of write processing requested by the first write request group. The first processor inserts a first barrier instruction into the issued requests, between the first write request group and the first completion write request. The first processor outputs all of the plurality of data write requests included in the first write request group, subsequently outputs the first barrier instruction, and subsequently outputs the first completion write request.

Abstract: A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting.

Abstract: One or more configuration state registers are provided in-memory rather than in-processor. A request to access a configuration state register is obtained. A determination is made that the configuration state register is in-memory rather than in-processor. Based on determining that the configuration state register is in-memory, the access is converted from an in-processor access operation to an in-memory access operation.

Abstract: An efficient data storage device is disclosed, which uses a microprocessor and at least one volatile memory to operate a non-volatile memory. The microprocessor allocates the volatile memory to provide a cache area. According to an asynchronous event request (AER) issued by a host, the microprocessor uses the cache area to collect sections of write data requested by the host, programs the sections of write data collected in the cache area to the non-volatile memory together, and reports failed programming of the sections of write data to the host by AER completion information.

Abstract: A memory system includes a controller, a buffer, and a nonvolatile memory including a plurality of blocks, wherein each of the blocks includes a plurality of pages and each of the pages includes a plurality of unit data portions. The controller is configured to carry out garbage collection by reading data from one or more pages of a target block of the garbage collection and selectively copying valid unit data portions included in the read data to another block, count a number of invalid unit data portions included in the read data, and accept, in the buffer, unit data portions from a host as write data, up to a number determined based on the counted number, during the garbage collection.

Abstract: Examples include techniques to manage cache resource allocations associated with one or more cache class of service (CLOS) assignments for a processor cache. Examples include flushing portions of an allocated cache resource responsive to reassignments of CLOS.

Abstract: An electronic system includes: a key value storage device, configured to transfer user data, the key value storage device including: a non-volatile memory array accessed by a key value address, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to reduce a number of copies of the user data in the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree, including a key value translation block, to access the user data.

Abstract: Systems and methods for predicting read commands and pre-fetching data when a memory device is receiving random read commands to non-sequentially addressed data locations are disclosed. A limited length sequence of prior read commands are generated and compared to a read command history datastore. When a prior pattern of read commands is found corresponding to the search sequence, a next read command that previously followed that search sequence may be used as a predicted next read command and data pre-fetched based on the read command data location information associated with that prior read command that is being used as the predicted read command.

Abstract: During a restart process in which metadata is loaded from at least one of a plurality of storage devices into a cache, a storage controller is configured to generate an IO thread in response to the receipt of an IO request, identify at least one metadata page of the metadata that is used to fulfill the IO request, and generate a loading thread in association with the received IO thread that is configured to cause the storage controller to perform prioritized loading of the identified at least one page of the metadata into the cache. The loading thread is detachable from the IO thread such that, in response to an expiration of the IO thread, the loading thread continues to cause the storage controller to perform the prioritized loading until the loading of the at least one page of the metadata into the cache is complete.

Abstract: Configurable architectural placement control. A control is provided that specifies a location in memory at which one or more in-memory configuration state registers are stored. The control is used to access an in-memory configuration state register of the one or more in-memory configuration state registers. The control may be a configuration state register in which a base address specifying the location in memory is included.

Abstract: Techniques to manage virtual memory are disclosed. In various embodiments, a time domain page access signal of a page is transformed to a frequency domain to obtain an access frequency. The access frequency is used to manage storage of the page in a page cache in memory. The access frequency may be used to evict the page from the page cache or, in some embodiments, to predictively load the page into the page cache.

Abstract: A real time file alteration sensing-based automatic backup device includes: a backup target selection unit selecting one or more backup targets that are accessible over a network and are subjected to backup; a content alteration sensing unit sensing in real time whether contents of the one or more backup targets are altered or scanning all the backup targets for sensing at particular-time intervals; a backup data generation unit generating, when the alteration of the content of the backup target is sensed, backup data containing information required for recovery of the sensed backup target; and a backup data storage unit storing the generated backup data.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device selects storage parameters for a multi-vault synchronization process from a first storage vault to a second storage vault. The computing device synchronizes storage of the set(s) of ingestion encoded data slices (EDSs) between the vaults and maintains storage of a portion of an ingestion data stream within the second storage vault. The computing device facilitates deletion of the set(s) of ingestion EDSs corresponding to the portion of an ingestion data stream from the first storage vault. the computing device performs additional multi-vault synchronization process(es) for any other portion(s) of the ingestion data stream.

Abstract: Embodiments of the present disclosure relates to data block processing in a distributed processing system. According to one embodiment of the present disclosure, a computer-implemented method is proposed. A first performance indicator for processing a data block by a first processing module is obtained, where the data block is loaded into the first processing module. Then, a second performance indicator for processing the data block by a second processing module is obtained, where the first and second processing modules being logical instances launched in a distributed processing system for processing data blocks. Next, one processing module is selected from the first and second processing modules for processing the data block based on a relationship between the first and second performance indicators.

Abstract: A set of device maintenance related data is received from each of a plurality of non-volatile memory modules. Each of the plurality of non-volatile memory modules comprise a plurality of non-volatile memory devices. Based at least in part on said set of device maintenance related data a maintenance operation to be performed is determined. The determined device maintenance related operation is performed.

Abstract: According to one embodiment of the present invention, an apparatus is disclosed. The apparatus includes a memory array having a plurality of memory cells. The apparatus further includes memory access circuits coupled to the memory array and configured to perform write operations responsive to control signals. The apparatus further includes control logic coupled to the memory access circuits and configured to apply a set of write parameters based, at least in part, on a number of write operations performed by the memory access circuits and further configured to provide control signals to the memory access circuits to perform write operations on the plurality of memory cells according to the set of write parameters.