Patents Examined by Mohamed M Gebril
  • Patent number: 10261900
    Abstract: A transmission device (300) comprising a data cache system is provided with a data acquisition part (315) for acquiring volume data indicating the volume of transactionable products or services transmitted from a server. The transmission device (300) is provided with a saving part (320) for saving the acquired volume data in an information memory (390) as cache data, and a request acquisition part (330) for acquiring requests seeking volume output. The transmission device (300) is provided with a determination part (350) for determining whether or not the cache data is valid based on the elapsed time from when the cache data was received or saved and the volume indicated by the cache data, when a request is acquired. When the determination is that the cache data is invalid, the data acquisition part (315) receives new volume data from the server, and the saving part (320) saves the new volume data as new cache data in the information memory (390).
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: April 16, 2019
    Assignee: Rakuten, Inc.
    Inventor: SeungHee Lee
  • Patent number: 10255203
    Abstract: Technologies for zero-copy inter-virtual-machine communication include a computing device with extended page table support. A sender virtual machine stores data in a shared memory block and enables access to protected code without generating a virtual machine exit, for example by executing a specialized processor instruction. From the protected code, the sender virtual machine sets a permission in an extended page table associated with the shared memory block and notifies a receiver virtual machine. When the permission is set, the sender virtual machine is prohibited from writing or executing the contents of the shared memory block. The receiver virtual machine reads data from the shared memory block and then enables access to protected code without generating a virtual machine exit. From the protected code, the receiver virtual machine clears the permission and notifies the sender virtual machine that reading is complete. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventor: Uri Elzur
  • Patent number: 10255190
    Abstract: Systems, apparatuses, and methods for implementing a hybrid cache. A processor may include a hybrid L2/L3 cache which allows the processor to dynamically adjust a size of the L2 cache and a size of the L3 cache. In some embodiments, the processor may be a multi-core processor and there may be a single cache partitioned into a logical L2 cache and a logical L3 cache for use by the cores. In one embodiment, the processor may track the cache hit rates of the logical L2 and L3 caches and adjust the sizes of the logical L2 and L3 cache based on the cache hit rates. In another embodiment, the processor may adjust the sizes of the logical L2 and L3 caches based on which application is currently being executed by the processor.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: April 9, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Gabriel H. Loh
  • Patent number: 10255181
    Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing on a computing device. Aspect methods may include offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode, detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator, and switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: April 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Edmund Turner, Bohuslav Rychlik
  • Patent number: 10254993
    Abstract: Provided are a computer program product, system, and method for selecting first data sets in a first storage group to swap with second data sets in a second storage group. First data sets are stored in a first storage group and second data sets are stored in a second storage group. A determination is made for a value for each of at least one of the first data sets based on at least one priority of at least one job processing I/O activity at the first data set. At least one of the first data sets for which the value was determined is selected to migrate to the second storage group based on the value.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyle B. Dudgeon, David C. Reed, Esteban Rios, Max D. Smith
  • Patent number: 10248565
    Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing a hybrid input/output (I/O) coherent write request on a computing device, including receiving an I/O coherent write request, generating a first hybrid I/O coherent write request and a second hybrid I/O coherent write request from the I/O coherent write request, sending the first hybrid I/O coherent write request and I/O coherent write data of the I/O coherent write request to a shared memory, and sending the second hybrid I/O coherent write request without the I/O coherent write data of the I/O coherent write request to a coherency domain.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: April 2, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Edmund Turner, Bohuslav Rychlik
  • Patent number: 10241928
    Abstract: For maintaining consistency for a cache that contains dependent objects in a computing environment, object dependencies for cached objects are managed by defining and maintaining object dependency lists for each one of the cached objects for identifying objects upon which the cached objects are dependent. Maintaining cache consistency for 2 types of cache eviction policies is supported by maintaining an object dependency lists for each one of the cached objects for identifying objects dependent upon the cached object. Each of the objects in an object dependency list is updated when the object is updated.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yariv Bachar, Aviv Kuvent, Asaf Levy, Konstantin Muradov
  • Patent number: 10241717
    Abstract: A data processing device including a processor and a memory interface, the processor being configured to control the refreshing of a memory by the steps of: periodically forming an estimate of a current rate of decay of a memory and updating an accumulated level of decay of the memory in dependence on the estimated current rate of decay; and causing the memory interface to refresh the memory when the accumulated level of decay exceeds a predetermined threshold. The estimate may be based on a measurement of ambient temperature.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: March 26, 2019
    Assignee: Qualcomm Technologies International, Ltd.
    Inventor: Neil Stewart
  • Patent number: 10169166
    Abstract: Techniques described herein include an event notification processing platform configured to process large-scale event notifications in relative real time. The platform may receive event notifications from multiple sources and publish them to an event stream, or log. The platform may subsequently process each notification at a processing module according to one or more sets of rules and the processed information may be made available via a data store. Rule sets may be selected based on the type of event received by the platform. A backup data store may record event notifications as they are received or at periodic intervals. Event notification data may also be stored at multiple levels of the platform, so that in the case of a failure of one or more components of the platform, data may continue to be processed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: January 1, 2019
    Assignee: BEIJING CHUANGXIN JOURNEY NETWORK TECHNOLOGY CO, LTD.
    Inventors: Xin Han, Jia Wen, Jianhua Wang, Zhijun Qiao, Jin Yu
  • Patent number: 10169241
    Abstract: A first cache of a first IOA is detected storing an amount of data that satisfies a memory shortage threshold. A request for extra memory for the first IOA is transmitted. The request is sent in response to detecting that the first cache stores the amount of data that satisfies the memory shortage threshold. The request is transmitted to a plurality of IOAs of a computer system. A second cache of a second IOA is detected storing an amount of data that satisfies a memory dissemination threshold. Memory of the second cache is allocated to the first cache. The memory is allocated in response to the request and the amount of data in the second cache satisfying the memory dissemination threshold.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Clark A. Anderson, Adrian C. Gerhard, William J. Maitland, Jr.