Abstract: Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime where nucleation probability of the PCM cells is enhanced prior to applying a subsequent SET programming signal. In one embodiment, the method includes applying a nucleation signal to the PCM cells to form nucleation sites within the memory array where the nucleation signal has a non-zero rising-edge. A programming signal is subsequently applied to achieve a desired level of crystallinity within selected ones of the plurality of PCM cells. Additional methods and apparatuses are also described.

Abstract: A semiconductor device may include a first internal command generation circuit, a first DLL circuit, a second internal command generation circuit, and a second DLL circuit. The first internal command generation circuit may generate a first delay command in response to a first external command, a first latency, a first clock, a first delay control signal, and a second clock. The first DLL circuit may generate the first delay control signal and the first second clock in response to the first clock. The second internal command to generation circuit may generate a second delay command in response to a second external command, a second latency, the first clock, a second delay control signal, and a third clock. The second DLL circuit may generate the second delay control signal and the third clock in response to the first clock.

Abstract: According to one embodiment, a memory device comprises a first memory cell configured to store data, a first word line connected to the first memory cell, a first circuit configured to supply a voltage to the first word line, a second circuit configured to control the first circuit, and a sequencer configured to control the first circuit and the second circuit. The sequencer, when data is written to the first memory cell, determines whether a condition is satisfied or not. The sequencer causes the second circuit to generate a first voltage, when the sequencer determines that the condition is not satisfied, and causes the second circuit to generate a second voltage which is higher than the first voltage, when the sequencer determines that the condition is satisfied.

Abstract: A memory device includes a first dynamic random access memory (DRAM) integrated circuit (IC) chip including first memory core circuitry, and first input/output (I/O) circuitry. A second DRAM IC chip is stacked vertically with the first DRAM IC chip. The second DRAM IC chip includes second memory core circuitry, and second I/O circuitry. Solely one of the first DRAM IC chip or the second DRAM IC chip includes a conductive path that electrically couples at least one of the first memory core circuitry or the second memory core circuitry to solely one of the first I/O circuitry or the second I/O circuitry, respectively.

Abstract: Apparatuses and methods for providing driving signals in semiconductor devices are described. An example apparatus includes a plurality of memory cell mats including a plurality of word lines and a word line driver coupled to the plurality of word lines of the plurality of memory cell mats. The word line driver is configured, responsive to a row active command, to provide a first voltage to a selected word line of the plurality of the word lines of a selected memory cell mat of the plurality of memory cell mats, provide a second voltage different from the first voltage to each of unselected word lines of the plurality of the word lines of the selected memory cell mats of the plurality of memory cell mats, and provide no voltage to each of the plurality of word lines of each of unselected memory cell mats of the plurality of memory cell mats.

Abstract: A method for forming 3D memory device includes forming an alternating dielectric stack in a contact region on a substrate, forming a plurality of contact holes with various depths vertically extending in the alternating dielectric stack, forming a sacrificial-filling layer to fill the contact holes, forming a plurality of dummy channel holes penetrating the alternating dielectric stack in the contact region, filling the dummy channel holes with a dielectric material to form supporters, and replacing the sacrificial layers of the alternating dielectric stack and the sacrificial-filling layer with conductive layers so as to form a plurality of gate lines and contacts.

Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material (SSM). Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.

Abstract: A high speed thin film two terminal resistive memory article of manufacture comprises a chargeable and dischargeable variable resistance thin film battery having a plurality of layers operatively associated with one another, the plurality of layers comprising in sequence, a cathode-side conductive layer, a cathode layer comprised of a material that can take up cations and discharge cations in a charging and discharging process, an electrolyte layer comprising the cations, a barrier layer, an anode layer, and an optional anode-side conductive layer, the barrier layer comprised of a material that substantially prevents the cations from combining with the anode layer.

Abstract: Cache mode for word lines where the cache mode utilizes an internal timer for a memory cell to disable connection of a voltage to a transistor of a word line driver of the memory cell before an end of a specified end of period. By early disconnection, the local controls of the memory cell may provide additional time to settle after disconnection of the voltage without interfering with operations (e.g., read, write, activate) of the memory cell, since the internal timer may be programmed to be greater than or equal to a worst case scenario for the operations.

Abstract: A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

Abstract: A semiconductor device may include a refresh control circuit which may generate test addresses that are counted based on a refresh signal and a detection clock signal and may senses logic levels of internal data corresponding to the test addresses to generate a sense signal. The semiconductor device may include a memory circuit may include a plurality of word lines which are selected by the test addresses and may output the internal data stored in memory cells connected to the word lines. The semiconductor device may include an address storage circuit may divide each of the test addresses into a main group and a sub-group to store the main groups and the sub-groups of the test addresses. The address storage circuit may store the sub-groups which are inputted at a point of time that the sense signal is generated, regarding the stored main groups having the same level combination.

Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.

Abstract: A method of operating a memory controller includes classifying a plurality of memory cells in an erase state into a plurality of groups, based on erase state information about the plurality of memory cells in the erase state; setting at least one target program state for at least some memory cells from among memory cells included in at least one of the plurality of groups; and programming the at least some memory cells for which the at least one target program state has been set, to a program state other than the at least one target program state from among the plurality of program states.

Abstract: A method of controlling memory devices of a memory controller, the memory devices including a plurality of memory dies, includes receiving at least one data operation request and a power budget from external of the memory controller; determining respective data operation times of the plurality of memory dies, wherein a power consumption due to at least one data operation in response to the at least one data operation request may be equal to or less than the power budget; and controlling the plurality of memory dies based on the data operation times.

Abstract: A data storage device includes a memory device and a controller. The memory device includes at least an MLC block. The MLC block includes a plurality of physical pages. The controller is coupled to the memory device. When the controller determines that a sudden power-off has occurred during a previous write operation for writing data onto the MLC block, the controller finds a predetermined page that has been attacked by the sudden power-off, double programs the predetermined page and a first page that is directly related to the predetermined page and dummy programs a plurality of second pages that are indirectly related to the predetermined page.

Abstract: A method is described. The method includes configuring first register space to establish ODT values of a data strobe signal trace of a DDR data bus. The method also includes configuring second register space to establish ODT values of a data signal trace of the DDR data bus. The ODT values for the data strobe signal trace are different than the ODT values for the data signal trace. The ODT values for the data strobe signal do not change when consecutive write operations of the DDR bus write to different ranks of a same DIMM.

Abstract: A non-volatile memory module includes an input/output buffer coupled to first and second signal transmission paths, and control circuitry coupled to the input/output buffer, the control circuitry being configured to receive a first signal on the first signal transmission path, receive a second signal on the second signal transmission path, determine a delay between the first signal and the second signal, generate a delay mismatch value based on the determined delay, and transmit the delay mismatch value on one or more signal transmission paths coupled to the input/output buffer.

Abstract: Some embodiments include an integrated assembly having a capacitor. The capacitor has a storage node configured as an upwardly-opening container shape. The container shape has a first side surface and a second side surface. The first and second side surfaces are along outer edges of the container shape and are in opposing relation to one another. The second side surface has a lower portion vertically overlapped by the first side surface, and has an upper portion which is not vertically overlapped by the first side surface. A middle-level lattice is adjacent to the first side surface and supports the first side surface. A higher-level lattice is adjacent to the second side surface and supports the second side surface. Some embodiments include integrated memory (e.g., DRAM).

Abstract: A matrix-vector multiplication device includes a memory crossbar array with row lines, column lines, and junctions. Each junction comprises a programmable resistive element and an access element. A signal generator is configured to apply programming signals to the resistive elements to program conductance values for the matrix-vector multiplication and a readout circuit is configured to apply read voltages to the row lines and to read out current values of the column lines. Control circuitry is configured to control the signal generator and the readout circuit and to select, via the access terminals, a plurality of resistive elements in parallel according to a predefined selection scheme which applies the signals and/or the read voltages in parallel to resistive elements which do not share the same row and column line and applies the programming signals and/or the read voltages to at most one resistive element per row line and column line.

Abstract: A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.