Abstract: Among other things, one or more systems and/or techniques for harvesting thermal energy for utilization by a dispensing system are provided herein. The dispensing system may comprise one or more thermal scavenging devices configured to collect thermal energy from a user. For example, a first thermal scavenging device, coupled to a top housing portion of the dispensing system, may collect thermal energy from a palm of a user hand; a second thermal scavenging device, coupled to a bottom housing portion of the dispensing system, may collect thermal energy from a top portion of the user hand; and/or other thermal scavenging devices may be operatively coupled to the dispensing system. In this way, the collected thermal energy is transformed into electrical energy for powering the dispensing system (e.g., powering a current dispense event, stored for a subsequent dispense event, validation of a refill container, detection of a user, etc.).

Abstract: A computer-implemented method for modifying an original design of an integrated circuit in accordance with an engineering change order (ECO) design includes cloning complex logic gate having multiple logic functions with cloned logic gates in parallel with the corresponding complex logic gates in the original design and the ECO design and expanding each cloned logic gate to corresponding base functionality logic gates to provide an expanded original design and an expanded ECO design using the processor. The method also includes modifying at least a portion of the expanded original design to have a circuit topology that is the same as the expanded ECO design in order to have an input from the expanded original design to an output structure be the same as the input from the expanded ECO design to the output structure in response to an expanded original design input and an expanded ECO design input being non-equivalent.

Abstract: Integrated circuits are manufactured using a direct write lithography step to at least partially form at least one layer within the integrated circuit. The performance characteristics of an at least partially formed integrated circuit are measured and then the layout design to be applied with a direct write lithography step is varied in dependence upon those performance characteristics. Accordingly, the performance of an individual integrated circuit, wafer of integrated circuits or batch of wafers may be altered.

Abstract: A system for verifying functionality of a circuit design under test (DUT) includes a control station comprising at least one graphical user interface (GUI); and at least one emulator in communication with the control station. The emulator may include a verification component and a register abstraction layer (RAL), wherein the verification component is configured to implement the DUT and the RAL is configured to implement one or more communication interfaces of the DUT. A traffic predictor in communication with the at least one emulator may monitor data traffic over the communication interface between the at least one emulator and the DUT, predict a response to the data traffic by the DUT, monitor a response to the traffic by the DUT, and determine if the response by the DUT matches the predicted response.

Abstract: In one embodiment, a method for improving the alignment of CAD data to optical imaging data, such as LSM and LVI images of integrated circuits is disclosed. Image reconstruction techniques are applied to optical images, such as laser voltage images (LVI), laser scanning microscope (LSM) images, or emission images, to produce reconstructed images which may have higher resolution, increased signal-to-noise, or other enhancements. Multiple CAD pattern layers are processed to generate second CAD images more closely corresponding to the appearance of the reconstructed images. Alignment of the reconstructed images to the second CAD data may be substantially more accurate and precise than alignment of the initial optical images to the CAD data—in some cases this improvement may make the difference between a successful alignment and a failed alignment.

Abstract: A passive electrical component is described including a substrate, at least a first, second and third electrically conductive pad, each disposed on the substrate and at least a first electrical device fixedly attached to the first pad and the second pad. The first electrical device is electrically connected to the first and second pads. The third pad is devoid of electrical connection to either the first or the second pads. The component is recognizable by both a Computer Aided Design program and an automated component assembly machine.

Abstract: A method for timing optimization is disclosed. The method includes obtaining information on detour locations of a chip by performing a routing operation, establishing, through machine learning, a model that describes a relationship between an image map and the detour locations, generating predicted detour locations based on the model and the image map, determining the probability of detouring in a region of the predicted detour locations, determining a predicted detour net for a path in a region having a high probability of detour, and determining sensitivity of the path.

Abstract: A method for optimizing manufacturability of standard cells includes generating random contexts for the standard cells, inserting vias into the standard cells, and performing a lithography verification on the standard cells after the vias have been inserted. The method enables early detection and resolution of potential hot spots on standard cell pin connections and reduction of hot spots that are introduced by the router at the chip level. The early detection and reduction of hot spots shortens the cycle time of a standard-cell based design.

Abstract: A method for making a multitude of masks for manufacturing an integrated circuit includes receiving the integrated circuit design printable using a multiple-patterning process. The design includes shapes and at least one layout conflict preventing decomposition of the design into the multitude of masks. The method further includes forming a subset of the shapes including the shapes associated with the at least one layout conflict. The method further includes categorizing the shapes of the subset into one of a multitude of topology types, generating stitch candidate solutions for the multitude of topology types, and decomposing the design into a multitude of masks. The subset of the multitude of shapes is formed by generating a first graph representative of the design, decomposing the first graph into at least three colors to form a colored graph; and identifying within the first graph, a second graph including at least one conflict edge.

Abstract: A method of inspecting patterns formed the manufacturing of semiconductor devices or the like includes producing an image of the patterns, producing a boundary image including a plurality of boundary patterns corresponding to first and second boundaries of each of the patterns, combining the pattern image and the boundary image to produce an overlapping image including overlapping patterns in which the patterns fill regions between the boundary patterns, and binarizing the overlapping image to produce a binary image including binary patterns corresponding to the overlapping patterns.

Abstract: A retractable cable or hose station can include a guide with a first pulley fixed with respect to a longitudinally extending track. The retractable cable or hose station can also include a trolley configured to travel along the track, where the trolley has at least a second pulley to be positioned in a line with the first pulley generally parallel to the longitudinally extending track. The retractable cable or hose station can also include a flexible cable or hose configured to be looped around the first pulley and the second pulley so that the trolley can be pulled toward the first pulley when a free end of the flexible cable or hose is pulled away from the first pulley. The retractable cable or hose station can include a biasing mechanism for biasing the trolley away from the first pulley to tighten and retract the flexible cable or hose.

Abstract: This application discloses a computing system to implement a place and route tool to synthesize a clock tree in a layout design of an integrated circuit based on timing constraints for the integrated circuit. The computing system can select a portion of the clock tree to present in a schematic connectivity presentation based on a conformance of the portion of the clock tree to timing constraints for the clock tree. The computing system can compress the other portions of the clock tree into the compacted representation based on the selection of the portion of the clock tree. The compacted representation can retain a hierarchical connectivity of the other portions of the clock tree. The computing system can generate the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree coupled to at least one compacted representation of other portions of the clock tree.

Abstract: A method for performing wireless charging control of an electronic device and an associated apparatus are provided, where the method includes: determining at least one random value for controlling timing of packet transmission regarding at least one wireless charging report of the electronic device; and based on the aforementioned at least one random value, sending at least one random phase-delay packet, wherein each random phase-delay packet of the aforementioned at least one random phase-delay packet has a random phase-delay with respect to a time slot, and the aforementioned at least one random phase-delay packet is utilized for carrying information of the aforementioned at least one wireless charging report. More particularly, a wireless charging device (e.g. transmitter pad) is arranged to wirelessly charge the electronic device, and based on the aforementioned at least one random value, the electronic device does not obtain information from the wireless charging device through any packet.

Abstract: A method, system, and computer program product include electronic design automation (EDA) tools used with standard CMOS processes to design and produce radiation-hardened (rad-hard) integrated circuits (ICs) having a predictable level of radiation hardness while maintaining a desired level of performance and tracking circuit area. The tools include rad-hard design rule checking (DRC) decks, rad-hard SPICE models, and rad-hard cell libraries. A rad-hard parasitic components extraction process makes use of rad-hard DRC rules to locate occurrences of parasitic devices, calculate their effects on circuit performance, and return this information to layout and circuit simulation tools. Changes to the layout are suggested and implemented with varying degrees of automation. Some of these tools can be provided as components of a rad-hard process design kit (PDK). They can be used in conjunction with commercial EDA tools to facilitate the incorporation of rad-hard features into new or existing IC designs.

Abstract: The invention relates to systems and methods for charging a vehicle. A vehicle and charging station can be designed such that an electric or hybrid vehicle can operate in a fashion similar to a conventional vehicle by being opportunity charged throughout a known route.

Abstract: A method of exhaustively verifying a property of a hardware design to implement a floating point power function. The method includes, formally verifying that the hardware design is recurrent over sets of ? input exponents, wherein ? is an integer that is a multiple of the reciprocal of the exponent of the power function; and for each recurrent input range of the hardware design, exhaustively simulating the hardware design over a simulation range to verify the property is true over the simulation range, wherein the simulation range comprises only ? input exponents.

Abstract: A system for generating low-power energy includes a fuel cell supplied by a gas network and a rechargeable energy storage system. An energy generation method and an energy management method implementing such an energy generation system are described.

Abstract: A system and method for providing an integrated circuit that integrates with and controls a device wherein the integrated circuit design is developed based on a selection of characteristics of the device. The system and method also provide software for establishing interoperability between the integrated circuit and a controller.

Abstract: A physical synthesis system includes a path straightening module, an ideal critical point identification (ID) module, and a free-space ID module. The path straightening module identifies at least one meandering critical path of a circuit, and generates a reference curve based on dimensions of the critical path. The ideal critical point ID module identifies at least one critical point on the reference curve. The free-space ID module identifies at least one free-space to receive a gate with respect to at least one critical point. The physical synthesis system further includes a free-space selector module and a gate modification module. The free-space selector module determines a modified slack timing value based on relocating the gate to the at least one free-space. The gate modification module moves the gate to the at least one free-space when the modified slack timing value is greater than an initial slack timing value.

Abstract: An apparatus and a method for charge control are provided. The apparatus for charge control may include an integrated direct current-to-direct current (DC/DC) converter configured to step up an output voltage level of a load to be greater than or equal to a supply voltage level set in a power amplifier, and the power amplifier configured to convert a direct current (DC) voltage stepped up by the integrated DC/DC converter into an alternating current (AC) voltage based on a resonant frequency, and to amplify the converted AC voltage. The apparatus for charge control may include a rectification unit configured to convert an AC power received wirelessly into a DC power; and a DC/DC converter configured to step down a voltage level of the DC power to a voltage level required by a load in the receiving mode.