Abstract: A computer system is provided that enables a designer of a circuit design to fracture and reconstitute a larger design for both computer modeling of the functionality and the physical implementation or rendering of the circuit design. More particularly, the designer may refine or re-work a sub-module of the larger sub-circuit without having to create a corresponding sub-module in the physical implementation. This capability thus avoids the significant complexity required for sub-module refinement in the current state of the art, and provides the designer with a much simpler flow.

Abstract: A power tool system includes a power tool, a power tool battery pack and a battery pack charger. The power tool battery pack is separable from and attachable to the power tool, and electrically connectable to the power tool electrical terminals when attached to the power tool. The power tool battery pack has at least one battery cell, a receiver coil, and a control circuit for controlling the amount of power that is provided to the at least one battery cell. The battery pack charger has at least one transmitter coil for generating a magnetic field which induces a voltage in the receiver coil, and a control circuit for controlling the amount of power that is provided to the transmitter coil.

Abstract: An electric vehicle quick charge control apparatus includes: a voltage detection unit for detecting the amplitude of a direct current voltage inputted from a charging station; a quick charging unit receiving a power applied from the charging station so as to quickly charge an electric vehicle battery and monitor the status of charge (SOC) information of the battery; and an integrated power control unit for dually controlling the quick charge of the battery on the basis of first discriminant information discriminated by determining the status of charge of the battery from the SOC information of the battery transmitted from the quick charging unit and second discriminant information discriminated by determining the status of charge of the battery from a detected voltage transmitted from the voltage detection unit.

Abstract: A battery pack includes a battery to supply power for a device and a battery management system (BMS) to manage the battery. A control current from the battery to the BMS is to be blocked based on a turn-off command.

Abstract: The present invention provides a system and computer implemented method for generating a layout of a cell defining a circuit component, the layout providing a layout pattern for a target process technology. In accordance with the method, a process technology independent layout representation associated with the circuit component is input, the process technology independent layout representation being defined within a grid array providing a plurality of grid locations. A mapping database is provided having a priority ordered list of mapping entries, each mapping entry storing a process technology independent layout section and an associated layout pattern section for the target process technology.

Abstract: Techniques and mechanisms for the use of layout-versus-schematic (LVS) design tools to validate photonic integrated circuit designs. Various implementations employ alternate analysis techniques with LVS analysis tools to perform one or more LVS analysis processes on photonic integrated circuits. These analysis processes may include curvilinear design validation and the associated flow implementations.

Abstract: Systems and methods are provided for identifying a wire of a plurality of wires to be adjusted to mitigate effects of electromigration. A method includes identifying a plurality of wires of a circuit, each wire comprising a one or more wire segments. An electromigration stress is determined for each wire path of each wire, a wire path being made up of one or more wire segments. For each wire, a highest determined electromigration stress is assigned for wire paths of that wire as the wire electromigration stress for that wire. An identification of the wire having the highest wire electromigration stress is stored, where the wire having the highest wire electromigration stress is a candidate for adjustment to mitigate electromigration effects.

Abstract: Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.

Abstract: An integrated circuit design may include registers and combinational logic. The registers may be reset using an original reset sequence. Integrated circuit design computing equipment may perform register moves within the circuit design, whereby registers are moved across one or more portions of the combinational logic. When moving the registers, counter values may be maintained for a group of non-justifiable elements within the combinational logic, across which the registers may move. The counter values may be maintained and updated on a per element, per clock domain basis to account for register moves across the corresponding non-justifiable elements. The maximum counter value for each clock domain may be chosen as an adjustment value that may be used to generate an adjustment sequence. The adjustment sequence may be prepended to the original reset sequence to generate an adjusted reset sequence that properly resets registers within the integrated circuit after registers moves.

Abstract: Techniques relate to dynamic complex fault model generation for diagnostics simulation and pattern generation. Inline fabrication parametric data is received, and the inline fabrication parametric data is a collection of physical measurements made on a device under test during a manufacturing fabrication of the device under test. A fault model of defects is generated according to the inline fabrication parametric data, where the fault model is based on a physical design of the device under test combined with the inline fabrication parametric data for the device under test. Test patterns are generated based on the fault model and the inline fabrication parametric data, such that the test patterns are configured to test the device under test in order to obtain results that are based on the inline fabrication parametric data. A simulation is run of the device under test using the results and the inline fabrication parametric data.

Abstract: A method for forming a contact plug layout include following steps. (a) Receiving a plurality of active region patterns and a plurality of buried gate patterns that are parallel with each other, and each active region pattern overlaps two buried gate patterns to form two overlapping regions and one contact plug region in between the two overlapping regions in each active region pattern; and (b) forming a contact plug pattern in each contact plug region, the contact plug pattern respectively includes a parallelogram, and an included angle of the parallelogram is not equal to 90°. The contact plug pattern in each active region pattern partially overlaps the two buried gate pattern, respectively. The step (a) to the step (b) are implemented using a computer.

Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

Abstract: A layout modification method is performed by at least one processor. The layout modification method includes: analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments; determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; and merging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level.

Abstract: A shopping cart that generates power, and comprising a shopping cart body; a set of wheels that each rotates about an axle coupled to the shopping cart body; a power generator that generates a source of power from a rotational force of the wheels when a user moves the shopping cart; a voltage regulator that controls the source of power output from the power generator; and an outlet for outputting the controlled power to an electronic device.

Abstract: The present disclosure is directed to systems and methods for using multiple libraries with different cell pre-coloring. In embodiments, the present disclosure determines a first set of cells to be placed using a single library methodology for pre-coloring and a second set of cells to be placed using a multiple library methodology for pre-coloring. In further embodiments, color-aware cell swapping can be performed based on the first set of cells and the second set of cells to align cells to swap the pre-coloring arrangements of cells to align with a track color of a closest legalization site candidate.

Abstract: An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across one or more portions of the combinational logic. The candidate registers to be retimed may have a different number or different types of secondary signals. In such scenarios, a selective modeling operation may be performed according to a predetermined precedence scheme to remove and model the differing secondary signals, thereby producing comparable registers with the same number and type of secondary signals. The comparable registers can then be retimed across the corresponding combinational logic. Backward or forward retiming operations may be performed in this way to achieve optimal circuit performance. During retiming adjacent combinational logic may also be combined to help minimize circuit area.

Abstract: A method, computerized system and computer program product for examining an object using a processor operatively connected to a memory, the method comprising: accommodating in the memory data indicative of a plurality of alignment targets, each alignment target associated with a target location on an object; accommodating in the memory a plurality of locations to be captured; and selecting by the processor an alignment target subset of the plurality of alignment targets, such that each of the plurality of locations is associated with and is within a determined distance from a single alignment target from the alignment target subset, the distance determined in accordance with a provided field of view, and wherein the alignment target subset comprises fewer targets than locations to be reviewed, the alignment target being usable for aligning the object relative to an examination tool for capturing the locations associated with the single alignment target.

Abstract: Systems and methods are provided for identifying a wire of a plurality of wires to be adjusted to mitigate effects of electromigration. A method includes identifying a plurality of wires of a circuit, each wire comprising a one or more wire segments. An electromigration stress is determined for each wire path of each wire, a wire path being made up of one or more wire segments. For each wire, a highest determined electromigration stress is assigned for wire paths of that wire as the wire electromigration stress for that wire. An identification of the wire having the highest wire electromigration stress is stored, where the wire having the highest wire electromigration stress is a candidate for adjustment to mitigate electromigration effects.

Abstract: A storage battery system connected to a power system includes: a storage battery; a BMU which monitors a state of the storage battery with a first sensor; a PCS which charges the storage battery and discharges from the storage battery with reference to an output value of a second sensor similar in type to the first sensor; and a control device. The control device receives a charge/discharge request and storage battery information supplied from the BMU and controls the PCS based on the charge/discharge request and the storage battery information. An abnormality detection unit of the control device acquires the output value of the second sensor from the PCS, and detects abnormality of any sensor as a result of comparison between the output value of the second sensor and an output value of the first sensor included in the storage battery information.

Abstract: In one embodiment, a method for building a clock tree for an integrated circuit design is provided. The clock tree may include a clock tree root node and a plurality of clock tree nodes that couple to sink pins for circuit elements of the integrated circuit design. The clock tree nodes may be arranged to distribute the clock signal to the sink pins. In synthesizing the clock tree, the sink pins may be clustered into one or more clusters. Clock tree nodes may be placed for the clock tree to distribute the clock signal to the one or more clusters. Timing information is determined to measure the clock signal delay from the root to the sink pins in the one or more clusters based on the placed one or more clock tree nodes. Different sets of timing information may be determined based on different sets of clock tree timing variation parameters. For example, the clock tree timing variation parameters includes timing information for multiple process corners and/or multiple modes of operation.