Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

Abstract: Provided is a semiconductor device comprising: a semiconductor substrate; a gate trench section that is provided from an upper surface to an inside of the semiconductor substrate and extends in a predetermined extending direction on the upper surface of the semiconductor substrate; a mesa section in contact to the gate trench section in an arrangement direction orthogonal the extending direction; and an interlayer dielectric film provided above the semiconductor substrate; wherein the interlayer dielectric film is provided above at least a part of the gate trench section in the arrangement direction; a contact hole through which the mesa section is exposed is provided to the interlayer dielectric film; and a width of the contact hole in the arrangement direction is equal to or greater than a width of the mesa section in the arrangement direction.

Abstract: A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.

Abstract: A method for manufacturing a photoelectric conversion element includes providing a base structure including a semiconductor substrate having a principal surface, a first electrode located on or above the principal surface, second electrodes which are located on or above the principal surface and which are one- or two-dimensionally arranged, and a photoelectric conversion film covering at least the second electrodes; forming a mask layer on the photoelectric conversion film, the mask layer being conductive and including a covering section covering a portion of the photoelectric conversion film that overlaps the second electrodes in plan view; and partially removing the photoelectric conversion film by immersing the base structure and the mask layer in an etchant.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure, disposed over the substrate; a gate structure, disposed over the substrate and covering a portion of the fin structure; a first sidewall, disposed over the substrate and surrounding a lower portion of the gate structure; and a second sidewall, disposed over the first sidewall and directly surrounding an upper portion of the gate structure, wherein the first sidewall is orthogonal to the second sidewall.

Abstract: A conductive, porous gallium-nitride layer can be formed as an active layer in a multilayer structure adjacent to one or more p-type III-nitride layers, which may be buried in a multilayer stack of an integrated device. During an annealing process, dopant-bound atomic species in the p-type layers that might otherwise neutralize the dopants may dissociate and out-diffuse from the device through the porous layer. The release and removal of the neutralizing species may reduce layer resistance and improve device performance.

Abstract: An image sensor including: a semiconductor substrate having a first region and a second region; an isolation region filling an isolation trench that partially penetrates the semiconductor substrate; a plurality of photoelectric conversion regions defined by the isolation region and forming a first hexagonal array on a plane that is parallel to a surface of the semiconductor substrate; and a plurality of microlenses respectively corresponding to the plurality of photoelectric conversion regions, and forming a second hexagonal array on the plane that is parallel to the surface of the semiconductor substrate.

Abstract: A switching device according to the present invention is a switching device for switching a load by on-off control of voltage, and includes an SiC semiconductor layer where a current path is formed by on-control of the voltage, a first electrode arranged to be in contact with the SiC semiconductor layer, and a second electrode arranged to be in contact with the SiC semiconductor layer for conducting with the first electrode due to the formation of the current path, while the first electrode has a variable resistance portion made of a material whose resistance value increases under a prescribed high-temperature condition for limiting current density of overcurrent to not more than a prescribed value when the overcurrent flows to the current path.

Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

Abstract: A submount on which a semiconductor device is mounted and which is mounted on a base made of metal, the submount including: a substrate; a first coating layer formed on a first surface of the substrate and made of a material having a higher coefficient of thermal expansion than that of the substrate; and a second coating layer formed on a second surface, positioned on a side opposite to the first surface, of the substrate and made of a material having a higher coefficient of thermal expansion than that of the substrate, in which a coating area of the second coating layer is smaller than a coating area of the first coating layer.

Abstract: A semiconductor substrate that is used as an underlying substrate for epitaxial crystal growth carried out by the HVPE method includes a ?-Ga2O3-based single crystal, and a principal plane that is a plane parallel to a [100] axis of the ?-Ga2O3-based single crystal. An epitaxial wafer includes the semiconductor substrate, and an epitaxial layer including a ?-Ga2O3-based single crystal and formed on the principal plane of the semiconductor substrate by epitaxial crystal growth using the HVPE method. A method for producing an epitaxial wafer includes by using the HVPE method, epitaxially growing an epitaxial layer including a ?-Ga2O3-based single crystal on a semiconductor substrate that includes a ?-Ga2O3-based single crystal and has a principal plane parallel to a [100] axis of the ?-Ga2O3-based single crystal.

Abstract: A flexible display substrate for a foldable display apparatus, a method of manufacturing the flexible display substrate, and a foldable display apparatus are disclosed. The flexible display substrate includes: a first region corresponding to a non-foldable region of the foldable display apparatus; a second region corresponding to a foldable region of the foldable display apparatus; a plurality of first pixel units disposed in the first region, configured to display an image, and each including a polysilicon thin film transistor; and a plurality of second pixel units disposed in the second region, configured to display an image, and each including an organic thin film transistor.

Abstract: The invention provides a method of manufacturing a SiC epitaxial wafer in which stacking faults are less likely to occur when a current is passed in a forward direction. The method of manufacturing the SiC epitaxial wafer includes a measurement step for measuring a basal plane dislocation density, a layer structure determining process for determining the layer structure of the epitaxial layer, and an epitaxial growth step for growing the epitaxial layers. And in the layer structure determination step, in the case of (i) when the basal plane dislocation density is lower than a predetermined value, the epitaxial layer includes a conversion layer and a drift layer from the SiC substrate side; and in the case of (ii) when the density is equal to or higher than the predetermined value, the epitaxial layer includes a conversion layer, a recombination layer, and a drift layer from the SiC substrate side.

Abstract: A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.

Abstract: A layer according to one embodiment of the present invention may exhibit a first number of electron states in a low-level electron energy range in a conduction band, and exhibit a second number of electron states in a high-level electron energy range higher than the low-level electron energy level in the conduction band, wherein localized states may exist between the low-level electron energy range and the high-level electron energy level.

Abstract: A method for forming a semiconductor arrangement includes forming a fin. A diffusion process is performed to diffuse a first dopant into the channel region of the fin. A first gate electrode is formed over the channel region of the fin after the first dopant is diffused into the channel region of the fin.

Abstract: A semiconductor device includes a folded drain extended metal oxide semiconductor (DEMOS) transistor. The semiconductor device has a substrate including a semiconductor material with a corrugated top surface. The corrugated top surface has an upper portion, a lower portion, a first lateral portion extending from the upper portion to the lower portion, and a second lateral portion extending from the upper portion to the lower portion. The folded DEMOS transistor includes a body in the semiconductor material, a gate on a gate dielectric layer over the body, a drift region contacting the body, and a field plate on a field plate dielectric layer, all extending continuously along the upper portion, the first lateral portion, the second lateral portion, and the lower portion of the corrugated top surface. Methods of forming the folded DEMOS transistor are disclosed.

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor layer; a source electrode, a drain electrode and a gate electrode located between the source electrode and the drain electrode disposed on a side of the semiconductor layer; at least two dielectrics located between the gate electrode and the drain electrode, wherein a dielectric coefficient of a dielectric adjacent to the gate electrode is greater than that of a dielectric away from the gate electrode and adjacent to the drain electrode.

Abstract: A mask-integrated surface protective tape for production of semiconductor chips, with the production containing steps (a) to (d), which tape comprises a base film and a mask material layer provided thereon, wherein a wetting tension of the base film on the side from which the mask material layer has been peeled is from 20.0 mN/m to 48.0 mN/m, and wherein a surface roughness Ra of the base film on the side from which the mask material layer has been peeled is within a range from 0.05 ?m to 2.0 ?m when measured in conformity to JIS B0601, (a) a specific laminating step; (b) a specific peeling step; (c) a specific plasma-dicing step; and (d) a specific ashing step.

Abstract: A semiconductor device includes a semiconductor layer, a gate electrode disposed on the semiconductor layer, a first dielectric layer disposed on the semiconductor layer and the gate electrode, a source field plate disposed on the semiconductor layer and the first dielectric layer, a second dielectric layer disposed on the source field plate, and a source electrode disposed on the second dielectric layer and electrically connected to the source field plate. The gate electrode has a first sidewall and a second sidewall respectively disposed on the first side and the second side. The source field plate extends from the first side to the second side. A portion of the source field plate is disposed to correspond to the second sidewall. The semiconductor device further includes a third dielectric layer disposed on the source electrode and a drain structure disposed on the second side.