Abstract: Embodiments of the present disclosure provide an array substrate including a base substrate, an active layer on the base substrate, a first gate insulating layer on the active layer, a first gate on the first gate insulating layer, and a second gate insulating layer on the first gate. The second gate insulating layer includes a first sub-insulating layer and a second sub-insulating layer disposed in a direction away from the active layer, and a hydrogen content of the first sub-insulating layer is larger than a hydrogen content of the second sub-insulating layer. A method for fabricating the array substrate and a display panel including the array substrate are also provided.

Abstract: Disclosed is a semiconductor memory device including a stack structure including layers which are vertically stacked on a substrate and each of which includes a bit line extending in a first direction and a semiconductor pattern extending in a second direction from the bit line, a gate electrode which is in a hole penetrating the stack structure and extending along a stack of semiconductor patterns, a vertical insulating layer covering the gate electrode and filling the hole, and a data storage element electrically connected to the semiconductor pattern. The data storage element includes a first electrode, which is in a first recess of the vertical insulating layer and has a cylindrical shape whose one end is opened, and a second electrode, which includes a first protrusion in a cylinder of the first electrode and a second protrusion in a second recess of the vertical insulating layer.

Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.

Abstract: A semiconductor chip may have a radiation-permeable support, a semiconductor body, and a transparent current spreading layer. The semiconductor body may have an n-sided semiconductor layer, a p-sided semiconductor layer, and an optically active area therebetween. The semiconductor body may be secured to the support by means of a radiation permeable connection layer. The current spread layer may be based on zinc selenide and may be adjacent to the n-sided semi-conductor layer. A method for producing this type of semiconductor chip is also disclosed.

Abstract: A method for forming a semiconductor device involves providing a semiconductor wafer having an active layer of a first conductivity type. First and second gates having first and second gate polysilicon are formed on the active layer. A first mask region is formed on the active layer. Between the first and second gates, using the first mask region, the first gate polysilicon, and the second gate polysilicon as a mask, a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, and first and second channel regions of the second conductivity type, are formed. In the active layer, using one or more second mask regions, first and second drift regions of the first conductivity type, first and second drain regions of the first conductivity type, and a source connection region of the second conductivity type, are formed.

Abstract: A method of forming a microelectronic device comprises forming a conductive shielding material over a conductive shielding structure and a first dielectric structure horizontally adjacent the conductive shielding structure. A second dielectric structure is formed on first dielectric structure and horizontally adjacent the conductive shielding material. The conductive shielding material and the second dielectric structure are patterned to form fin structures extending in parallel in a first horizontal direction. Each of the fin structures comprises two dielectric end structures integral with remaining portions of the second dielectric structure, and an additional conductive shielding structure interposed between the two dielectric end structures in the first horizontal direction. Conductive lines are formed to extend in parallel in the first horizontal direction and to horizontally alternate with the fin structures in a second horizontal direction orthogonal to the first horizontal direction.

Abstract: A thin film transistor, comprising a substrate, an active layer disposed on the substrate, and a source and drain that make electrical contact with the active layer, wherein the source and drain each comprise a first sub-electrode and a second sub-electrode that are stacked along a thickness of the active layer, and the first sub-electrode is closer to the active layer relative to the second sub-electrode. An area of an overlapping region between an orthographic projection of the second sub-electrode of at least one of the source and drain on the substrate and an overlapping region between an orthographic projection of the first sub-electrode of the at least one of the source and the drain on the substrate and the orthographic projection of the active layer on the substrate.

Abstract: A gate controlled semiconductor device comprising a collector region of a first conductivity type; a drift region of a second conductivity type located over the collector region; a body region of a first conductivity type located over the drift region; at least one first contact region of a second conductivity type located above the body region and having a higher doping concentration compared to the body region. The device further comprises at least one second contact region of a first conductivity type located laterally adjacent to the at least one first contact region, the at least one second contact region having a higher doping concentration than the body region. The device further comprises at least one active trench extending from a surface into the drift region, in which the at least one first contact region adjoins the at least one active trench so that, in use, a channel region is formed along said at least one active trench and within the body region.

Abstract: Provided are a thin film transistor structure, a manufacturing method thereof, and a display device. The method comprises: providing a substrate (10), and sequentially forming a gate (20), a gate insulating layer (30), an active layer (40), a doped layer (50), a source (610), a drain (620) and a channel region (70) on the substrate (10); placing the channel region (70) in a preset gas atmosphere for heating treatment; wherein, the channel region (70) is placed in a nitrogen atmosphere to heat for a first preset time, in a mixed atmosphere of nitrogen and ammonia to heat for a second preset time, in an ammonia atmosphere to heat for a third preset time; or first heating the channel region (70) for a fourth preset time, finally placing in the ammonia atmosphere to heat for a fifth preset time.

Abstract: According to one embodiment, a semiconductor device includes a substrate, a plurality of insulating films and a plurality of electrode films provided alternately on the substrate. The semiconductor device further includes a first insulating film, a first charge storage film, a third insulating film, a second charge storage film, a second insulating film, and a first semiconductor film that are sequentially provided along at least one side surface of each of the electrode films. The first charge storage film includes either (i) molybdenum, or (ii) titanium and nitrogen, and the second charge storage film includes a semiconductor film.

Abstract: A method of depositing a SiN film onto a flexible substrate includes providing the flexible substrate, and depositing the SiN film onto the flexible substrate in a plasma enhanced chemical vapour deposition (PECVD) process using SiH4, N2 and H2, in which the temperature of the substrate is 200° C. or less and SiH4 is introduced into the PECVD process at a flow rate of greater than 100 sccm.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor layer, a second semiconductor layer, and a first insulating layer. A position of the third electrode in a first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor layer includes Alx1Ga1-x1N and includes a first partial region, a second partial region, and a third partial region. The second semiconductor layer includes Alx2Ga1-x2N. A portion of the second semiconductor layer is between the third partial region and the third electrode in the second direction. The first insulating layer includes a first insulating region. The first insulating region is between the third electrode and the portion of the second semiconductor layer in the second direction.

Abstract: A semiconductor device including an insulating layer on a substrate; channel semiconductor patterns stacked on the insulating layer and vertically spaced apart from each other; a gate electrode crossing the channel semiconductor patterns; source/drain regions respectively at both sides of the gate electrode and connected to each other through the channel semiconductor patterns, the source/drain regions having concave bottom surfaces; and air gaps between the insulating layer and the bottom surfaces of the source/drain regions.

Abstract: The present disclosure provides a thin film transistor, including: an active layer, a source and a drain electrically coupled with the active layer, and a plurality of doped layers located between the source and the active layer and between the drain and the active layer, a resistance of one of the plurality of doped layers farthest away from the active layer is smaller than that of any other doped layer. The disclosure further provides a gate driving circuit, a display substrate and a display device. With the present disclosure, current loss of a current passing through the doped layers of the thin film transistor is reduced, on-state current of the thin film transistor is improved and a situation that output signals of the thin film transistor are insufficient is avoided.

Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening.

Abstract: A light emitting device includes a substrate, a demarcating member and a light-diffusing plate. The substrate has a plurality of light sources. The demarcating member includes a plurality of wall parts defining a plurality of compartments respectively corresponding to the light sources with each of the light sources being surrounded by corresponding ones of the wall parts defining a single compartment. Each of the wall parts include a ridge part and an inclined surface part. The light-diffusing plate is disposed above the light sources and having a plurality of first protrusions disposed on a first surface of the light-diffusing plate facing the substrate. Each of the first protrusions overlaps the inclined surface part of each of corresponding ones of the wall parts in a plan view. Each of the first protrusions surrounds a corresponding one of the light sources in the plan view.

Abstract: A method of manufacturing a low temperature polysilicon thin film includes: forming a buffer layer on a substrate; forming a first silicon layer on the buffer layer; forming a second silicon layer on the first silicon layer, and forming a substrate impurity barrier interface between the first silicon layer and the second silicon layer, wherein the second silicon layer is thicker than the first silicon layer; and annealing the first silicon layer and the second silicon layer to form a polysilicon layer.

Abstract: A high-electron mobility transistor (HEMT) includes a substrate, a group III-V channel layer, a group III-V barrier layer, a group III-V cap layer, a source electrode, a first drain electrode, a second drain electrode, and a connecting portion. The group III-V channel layer, the group III-V barrier layer, and the group III-V cap layer are sequentially disposed on the substrate. The source electrode is disposed at one side of the group III-V cap layer, and the first and second drain electrodes are disposed at another side of the group III-V cap layer. The bottom surface of the first drain electrode is separated from the bottom surface of the second drain electrode, and the composition of the first drain electrode is different from the composition of the second drain electrode. The connecting portion is electrically coupled to the first drain electrode and the second drain electrode.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a barrier layer disposed above the substrate, and a dielectric layer disposed on the barrier layer and defining a first recess. The semiconductor device further includes a spacer disposed within the first recess and a gate disposed between a first portion of the spacer and a second portion of the spacer, wherein the gate defining a first recess.

Abstract: A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.