Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

Abstract: A thin-film device includes a polysilicon element and an oxide semiconductor element. The polysilicon element includes a first part made of low-resistive polysilicon. The oxide semiconductor element includes a second part made of low-resistive oxide semiconductor. The first part and the second part are disposed to overlap each other and connected.

Abstract: A high electron mobility transistor (HEMT) device and a manufacturing method thereof are provided. The HEMT device includes a channel layer, a barrier layer, a first gate electrode, a first drain electrode and a first source electrode. The channel layer is disposed on a substrate. A surface of a portion of the channel layer within a first region of the HEMT device includes a polar plane and a non-polar plane. The barrier layer is conformally disposed on the channel layer. The first gate electrode is disposed on the barrier layer, and located within the first region. The first drain electrode and the first source electrode are disposed within the first region, and located at opposite sides of the first gate electrode.

Abstract: The disclosure relates to a thin film transistor. The thin film transistor may include a substrate, an active layer on the substrate, a gate on the active layer, and a source and a drain. The active layer may include a first conducting region, a second conducting region, and a channel region between the first conducting region and the second conducting region. An orthographic projection of the source and an orthographic projection of the drain on the substrate may cover at least an orthographic projection of a first conducting region and an orthographic projection of a second conducting region on the substrate.

Abstract: The present disclosure provides a TFT array substrate and a manufacturing method thereof. For the manufacturing method, a source electrode and a drain electrode are formed at first, and then edges of the source electrode and the drain electrode are used as masks to pattern a semiconductor layer to form an amorphous silicon island, which makes edges of the amorphous silicon island flush with the edges of the source electrode and the drain electrode, and completely removes the exposed semiconductor layer outside a metal layer, thereby decreasing photoelectric sensitivity of a TFT device, decreasing a size of the TFT device, and being beneficial for saving layouts and simplifying processes.

Abstract: A thin film transistor, method of manufacturing the thin film transistor, an array substrate comprising the thin film transistor, and a display device comprising the array substrate. The thin film transistor comprises a substrate; a first electrode on the substrate; an active layer on a side of the first electrode away from the substrate; and a second electrode on a side of the active layer away from the first electrode. The first electrode and the second electrode are connected to the active layer, respectively. are also disclosed.

Abstract: A method of manufacturing an array substrate includes: forming a first semiconductor pattern and a first insulating layer group sequentially on a base substrate; forming a second semiconductor pattern and a second insulating layer group sequentially on the first insulating layer group; forming two first via holes in the first insulating layer group and the second insulating layer group to expose the first semiconductor pattern, annealing the exposed first semiconductor pattern and then removing an oxide layer on a surface of the first semiconductor pattern; forming connecting wires in the first via holes; forming second via holes in the second insulating layer group to expose the second semiconductor pattern, and forming a first source electrode and a first drain electrode in the second via holes such that the first source electrode or the first drain electrode covers and is connected to one of the connecting wires.

Abstract: The present disclosure provides a thin film transistor, a method for preparing the same, a display substrate, and a display device. The thin film transistor includes a gate electrode, a semiconductor layer, and a gate insulation layer arranged between the gate electrode and the semiconductor layer, and the gate insulation layer includes a metal oxide layer and a modified layer formed through self-assembling on a side of the metal oxide layer away from the gate electrode and.

Abstract: Strained thin film transistors are described. In an example, an integrated circuit structure includes a strain inducing layer on an insulator layer above a substrate. A polycrystalline channel material layer is on the strain inducing layer. A gate dielectric layer is on a first portion of the polycrystalline channel material. A gate electrode is on the gate dielectric layer, the gate electrode having a first side opposite a second side. A first conductive contact is adjacent the first side of the gate electrode, the first conductive contact on a second portion of the polycrystalline channel material. A second conductive contact adjacent the second side of the gate electrode, the second conductive contact on a third portion of the polycrystalline channel material.

Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.

Abstract: A semiconductor memory device is provided. The device may include a lower gate line provided on a substrate and extended in a first direction, an upper gate line vertically overlapped with the lower gate line and extended in the first direction, a first capacitor provided between the lower gate line and the upper gate line, a second capacitor provided between the lower gate line and the upper gate line and spaced apart from the first capacitor in the first direction, a lower semiconductor pattern provided to penetrate the lower gate line and connected to the first capacitor, an upper semiconductor pattern provided to penetrate the upper gate line and connected to the second capacitor, and a lower insulating pattern provided between the second capacitor and the lower gate line to cover the entire region of a bottom surface of the second capacitor.

Abstract: Provided are a high electron mobility transistor and a method of manufacturing the high electron mobility transistor. The high electron mobility transistor includes a gate electrode provided on a depletion forming layer. The gate electrode includes a first gate electrode configured to form an ohmic contact with the depletion forming layer, and a second gate electrode configured to form a Schottky contact with the depletion forming layer.

Abstract: A method for manufacturing a semiconductor package includes the following steps. A semiconductor process is performed to form an encapsulated semiconductor device, wherein the encapsulated semiconductor device comprises an encapsulating material and a semiconductor device encapsulated by the encapsulating material. A testing apparatus including a holder body, a positioning mechanism and a force applying bar is provided. The encapsulated semiconductor device is clamed by the holder body. A clamping position of the encapsulated semiconductor device is adjusted by the positioning mechanism. The positioning mechanism is removed. A predetermined force is applied to a part of the encapsulated semiconductor device exposed by the holder body by the force applying bar. If the encapsulated semiconductor device is failed by the predetermined force, a process parameter of the semiconductor process is modified to form a modified encapsulated semiconductor device.

Abstract: An Enhancement Mode (e-mode) Metal Insulator Semiconductor (MIS) High Electron Mobility Transistor (HEMT), or EMISHEMT, with GaN channel regrowth under a gate area, is described. The EMISHEMT with GaN channel regrowth under a gate area provides a normally-off device with a suitably high and stable threshold voltage, while providing a low gate leakage current. A channel layer provides a 2DEG and associated low on-resistance, while a channel-material layer extends through an etched recess and into the channel layer, and disrupts the 2DEG locally to enable the normally-off operation.

Abstract: A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.

Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

Abstract: An array substrate and a method of manufacturing the same are provided. The array substrate includes a substrate, a plurality of thin film transistors disposed on the substrate, and a planarization layer covering the plurality of thin film transistors and filled a region defined by the plurality of thin film transistors and the substrate.

Abstract: A method includes: providing a semiconductor body having a generation plane and crystal lattice planes which intersect the generation plane at intersecting lines; generating modifications in the semiconductor body by multiphoton excitation and which are spaced apart from one another, the modifications altering a physical property of the semiconductor body so as to form subcritical cracks in the generation plane; and separating a solid-state layer from the semiconductor body by connecting the subcritical cracks in the generation plane.

Abstract: Systems, methods, and apparatuses are provided for digit line formation for horizontally oriented access devices.