Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory comprises a plurality of magnetoresistive memory devices, wherein each magnetoresistive memory device includes a fixed magnetic region, a free magnetic region, and an intermediate region disposed in between the fixed and free magnetic regions. The magnetoresistive memory further comprises a first conductor extending adjacent each magnetoresistive memory device of the plurality of magnetoresistive devices, wherein the first conductor is in electrical contact with the free magnetic region of each magnetoresistive memory device.

Abstract: The present disclosure relates to a display screen and a display device integrated with the same. The display screen includes: a screen body having an active display area defined by a contour line, and a cover plate covering the screen body. The cover plate has a cover area corresponding to corners of the active display area, and the cover area covers the corners.

Abstract: The present disclosure provides a thin film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor includes: an active layer located on one side of the substrate; a first interlayer dielectric layer located on one side of the active layer away from the substrate; a source penetrating through the first interlayer dielectric layer, and connected to the active layer; a second interlayer dielectric layer located on one side of the first interlayer dielectric layer away from the active layer and covering the source; and a drain, wherein the drain comprises a first portion penetrating through the second interlayer dielectric layer and the first interlayer dielectric layer and connected to the active layer.

Abstract: A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.

Abstract: In an effective region of an active region, a main semiconductor element and a source pad thereof are disposed. A non-operating region of the active region excludes the effective region and is a high-function region in which a gate pad of the main semiconductor element and other electrode pads are disposed. An edge termination region and the electrode pads are separated by an interval equivalent to at least a width of one unit cell of the main semiconductor element. In the high-function region, at a border of the edge termination region, a lead-out electrode is provided on a front surface of a semiconductor substrate. The lead-out electrode has a function of leading out displacement current that flows to the high-function region from the edge termination region when the main semiconductor element is OFF. Thus, destruction at the edge termination region may be suppressed.

Abstract: The present disclosure provides a thin film transistor, a pixel structure, a display device, and a manufacturing method. The thin film transistor includes: a gate on the substrate; a gate insulating layer covering the gate and the substrate; a first support portion and a second support portion, which are provided on the gate insulating layer covering the substrate and located on both sides of the gate, wherein the first support portion is not connected to the second support portion; a semiconductor layer on the first support portion, the second support portion, and the gate insulating layer covering the gate; and a source and a drain respectively connected to the semiconductor layer. The first support portion and the second support portion are respectively configured to support the semiconductor layer.

Abstract: An imaging device including a semiconductor substrate including a pixel region and a peripheral region; an insulating layer covering the pixel and peripheral regions; first electrodes located on the insulating layer above the pixel region; a photoelectric conversion layer covering the first electrodes; a second electrode that covers the photoelectric conversion layer; detection circuitry electrically connected to the first electrodes; peripheral circuitry electrically connected to the detection circuitry, and; and a third electrode located on the insulating layer.

Abstract: [Object] The present disclosure relates to an image pickup device, an image pickup apparatus, and a production apparatus and method with which protection performance of an organic film can be improved. [Solving Means] An image pickup device according to the present disclosure includes: a photoelectric conversion device that photoelectrically converts incident light that has entered from outside; an organic film that is formed by being laminated on a light-incident surface side of the photoelectric conversion device; and an inorganic film that is formed by being laminated on a light-incident surface and side surfaces of the organic film and seals the organic film, the side surfaces of the organic film being tilted by an angle at which a thickness of the inorganic film that is formed by being laminated on the side surfaces becomes a predetermined thickness. The present disclosure is applicable to an image pickup device, an image pickup apparatus, a production apparatus for an image pickup device, and the like.

Abstract: A method of forming a crystallized semiconductor layer includes forming an insulating crystallization inducing layer on a base substrate; forming a semiconductor material layer on a side of the insulating crystallization inducing layer away from the base substrate by depositing a semiconductor material on the insulating crystallization inducing layer, the semiconductor material being deposited at a deposition temperature that induces crystallization of the semiconductor material; forming an alloy crystallization inducing layer including an alloy on a side of the semiconductor material layer away from the insulating crystallization inducing layer; and annealing the alloy crystallization inducing layer to further induce crystallization of the semiconductor material to form the crystallized semiconductor layer.

Abstract: A compound semiconductor device includes a semiconductor multilayer structure including an electron transit layer and an electron supply layer of a compound semiconductor; a source electrode, a gate electrode, and a drain electrode that are disposed above the semiconductor multilayer structure and are aligned in a first direction; a first insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the drain electrode, and has a tensile stress; a second insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the source electrode, and has a compressive stress; and a protective film that is formed between the first insulating film and the semiconductor multilayer structure, and between the second insulating film and the semiconductor multilayer structure.

Abstract: The present disclosure relates to a manufacturing method of LTPS TFT substrate and the LTPS TFT substrate. With respect to the manufacturing method, after the gate insulation layer is formed, the gate insulation layer is doped with nitrogen by a plasma containing nitrogen so as to increase the positive charges within the gate insulation layer. As such, the P-type TFT threshold voltage can be negatively shifted so as to enhance the splash screen issue.

Abstract: A semiconductor device includes a thin film transistor 101 including: a semiconductor layer 4 provided on a gate electrode 2 with a gate insulating layer 3 therebetween, wherein the semiconductor layer includes a first region Rs, a second region Rd, and a source-drain interval region RG that is located between the first region and the second region and overlaps with the gate electrode as seem from a direction normal to a substrate; a protection layer 5 arranged on the semiconductor layer 4; a first contact layer Cs in contact with the first region and a second contact layer Cd in contact with the second region; a source electrode 8s; and a drain electrode 8d, wherein: the semiconductor layer 4 includes a crystalline silicon region 4p, and at least a portion of the crystalline silicon region 4p is located in the source-drain interval region RG; and at least one opening 10 is provided that runs through the protection layer 5 and the semiconductor layer 4 and reaches the gate insulating layer 3, wherein the at l

Abstract: Provided is a thin film transistor. The thin film transistor includes a substrate, a channel part extending on the substrate in a first direction parallel to an upper surface of the substrate, source/drain electrodes connected to both ends of the channel part in the first direction, and a gate electrode spaced apart from the channel part in a second direction intersecting the first direction and parallel to the upper surface of the substrate. Each of the channel part, the source/drain electrodes, and the gate electrode is provided as a single layer.

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductive tier, a first insulator tier above the conductive tier, a sacrificial material tier above the first insulator tier, and a second insulator tier above the sacrificial material tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the second insulator tier. Channel material is formed through the insulative tiers and the wordline tier. Horizontally-elongated trenches are formed through the stack to the sacrificial material tier. Sacrificial material is etched through the horizontally-elongated trenches selectively relative to material of the first insulator tier and selectively relative to material of the second insulator tier. A laterally-outer sidewall of the channel material is exposed in the sacrificial material tier. A conductive structure is formed directly against the laterally-outer sidewall of the channel material in the sacrificial material tier.

Abstract: Disclosed is a semiconductor device for improving a gate induced drain leakage and a method for fabricating the same, and the semiconductor device includes a substrate, a first doped region and a second doped region formed to be spaced apart from each other by a trench in the substrate, a first gate dielectric layer over the trench, a lower gate over the first gate dielectric layer, an upper gate over the lower gate and having a smaller width than the lower gate, and a second gate dielectric layer between the upper gate and the first gate dielectric layer.

Abstract: The present invention relates to a conductive paste composition for solar photovoltaic cells comprising metal particles dispersed in a suitable carrier therefor, wherein said carrier comprises a solvent and a resin, and wherein at least a portion of said metal particles are characterized by having a ? value, as defined by X-ray diffraction<0.0020, having at least 50% degree of crystallinity, and being anisotropic with respect to crystallographic direction.

Abstract: A die attach system is provided. The die attach system includes: a support structure for supporting a substrate; a die supply source including a plurality of die for attaching to the substrate; a bond head for bonding a die from the die supply source to the substrate, the bond head including a bond tool for contacting the die during a transfer from the die supply source to the substrate; a first motion system for moving the bond head along a first axis; and a second motion system, independent of the first motion system, for moving the bond tool along the first axis.

Abstract: To provide a semiconductor device including an electrode having a low contact resistance with the back surface of a GaN substrate and being suitably bonded with solder, and having a low electric resistance of the current flowing in a vertical direction. The semiconductor device has a GaN substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a body electrode, a drain electrode, a source electrode, and a gate electrode. The drain electrode has a Ti layer, an Al layer, a Ti layer, a TiN layer, a Ti layer, a Ni layer, and an Ag layer sequentially from the second surface of the GaN substrate.

Abstract: An insulated gate field effect bipolar transistor (IGFEBT) includes a substrate, a deep well (DW) region, a first conductivity type well region, a gate structure, a source region and a drain region located on the first conductivity type well region at both sides of the gate structure, an anode, and a cathode. The source region includes a first doped region and a second doped region between the first doped region and the gate structure, and the drain region includes a third doped region and a fourth doped region formed on the third doped region. The substrate, the first and fourth doped regions are of the first conductivity type, and the DW region, the second and the third doped regions are of a second conductivity type. The anode is electrically coupled to the fourth doped region, and the cathode is electrically coupled to the first and second doped regions.

Abstract: A semiconductor device includes an active region defined by an element isolation region in a base substrate, source and drain regions of a first conductivity type spaced apart from each other, and formed in the active region, a body region of a second conductivity type surrounding the source region, and formed in the base substrate, a drift region of the first conductivity type surrounding the drain region, having a lower impurity concentration than the drain region, and formed in the base substrate, an insulating structure including a buried insulating pattern and a semiconductor pattern sequentially stacked on the drift region, a gate dielectric film including a first portion extending along an upper surface of the body region and a second portion extending along a side surface and an upper surface of the insulating structure, and a gate electrode extending along an upper surface of the gate dielectric film.