Patents Examined by Mohammed Rehman
  • Patent number: 9141165
    Abstract: A method of controlling the clock frequency of a processor executing software in a plurality of active periods, the method comprising, for each period: supplying to a power management application at least one parameter defining an execution profile for the period having high frequency and low frequency operating intervals; the power management application determining, based on said profile, granted clock frequencies for the high and low frequency operating intervals; the processor supplying to the power management application at the commencement of a period an operating cycle requirement for the period; the power management application determining, for each period, based on the operating cycle requirement, the length of the low frequency interval; and controlling the clock frequency in each interval based on the granted clock frequencies determined by the power management application.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: September 22, 2015
    Assignee: Icera Inc.
    Inventors: Peter Cumming, Hlond Marcin
  • Patent number: 9134788
    Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 15, 2015
    Assignee: Intel Corporation
    Inventors: Anupama Suryanarayanan, Matthew C. Merten, Ryan L. Carlson, Stephen H. Gunther
  • Patent number: 9098270
    Abstract: A device is configured to establish first and second device power domains. Isolation circuits isolate signals from passing between circuits in the first device power domain and circuits in the second device power domain. During a transition between power domains, an n-bit value is stored in a particular storage location, and compared to a particular n-bit value. Isolation between the first and second device power domains is removed when the n-bit value stored in the particular storage location matches the particular n-bit value.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 4, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Srikanth—Reddy Tiyyagura, David Still
  • Patent number: 9087114
    Abstract: An electrical current (“EC”) manager module may assign a plurality of hardware elements of the PCD to one of two groups. The EC manager module may monitor individual electrical current levels of one of the groups as well as calculate an instantaneous electrical current level for the PCD based on a current charge status for the PCD. The EC manager module may then adjust operation of at least one hardware element to keep operation of the PCD below the calculated instantaneous electrical current level for the PCD. The EC manager module may estimate an electrical current level for one of the groups based on requests issued to hardware elements. The EC manager module may also compare the calculated instantaneous electrical current level to the monitored electrical current level. The calculated instantaneous electrical current level may be compared to minimum current levels listed in a table.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: July 21, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Chun, Amy Derbyshire, Jon J. Anderson, Christopher Patrick, Todd Sutton, Eric Ian Mikuteit
  • Patent number: 9075610
    Abstract: An apparatus, method and system is described herein for thread consolidation. Current processor utilization is determined. And consolidation opportunities are identified from the processor utilization and other exaction parameters, such as estimating a new utilization after consolidation, determining if power savings would occur based on the new utilization, and performing migration/consolidation of threads to a subset of active processing elements. Once the consolidation is performed, the non-subset processing elements that are now idle are powered down to save energy and provide an energy efficient execution environment.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 7, 2015
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Efraim Rotem, Avinash N. Ananthakrishnan, Alon Naveh, Hisham Abu Salah, Nadav Shulman
  • Patent number: 9060097
    Abstract: A method to manage the power setting of a receiver/decoder for pay-TV comprising a timer and means to receive management messages, the power setting comprising at least three states, the active state during which the reception and the decoder is active, the active/standby state during which the receiver is active for the reception of management messages and the standby state during which the receiver/decoder is in idle mode.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 16, 2015
    Assignee: NAGRAVISION S.A.
    Inventor: Bertrand Wendling
  • Patent number: 9052896
    Abstract: In one embodiment, when a computing system is in a first state, a first set of inputs from one or more first sensors is detected. A first sensor value array is generated, and the first value array is fed as input to a first function generated by a first neural network. One or more first output values are calculated based on the first function, and a determination is made based on these first output values if a first action has occurred. If a first action has occurred, a second sensor value array is generated from a second set of inputs from one or more second sensors. The second sensor value array is fed as input to a second function generated by a second neural network. One or more second output values are calculated based on the second function, and the first state is exited based on these second output values.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: June 9, 2015
    Assignee: Facebook, Inc.
    Inventors: Benoit M. Schillings, David Harry Garcia
  • Patent number: 9037879
    Abstract: A rack server system including at least one server and a battery backup unit (BBU) is provided. A power supplier is coupled to the server for converting an input voltage into a first output voltage when the input voltage is normal and for providing the first output voltage to the server. The BBU is coupled to the server and the power supplier for detecting the first output voltage outputted from the power supplier and for providing a second output voltage to the server when the input voltage and/or the first output voltage are abnormal.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: May 19, 2015
    Assignee: Quanta Computer Inc.
    Inventors: Maw-Zan Jau, Tzu-Hung Wang, Chin-Hsiang Chan
  • Patent number: 9032193
    Abstract: A lightweight embedded directory server with portable LDAP data is disclosed. The directory server and database comprises a processing chip, an on-chip processing unit, an on-chip memory system, and an on chip input/output system. The memory system stores an embedded operating system and an embedded directory server, and is also used for storing data to be processed by the processing unit. The input/output system is provided for connecting the processor chip to one or more applications for supplying directory services to the one or more applications. A portable memory device stores a directory database, and, in use, this memory device is releasably connected to the on chip input/output system. An on-chip driver is used to perform read and write operations on the portable memory device; and a boot loader software program is used for starting execution of the embedded directory service.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chandrajit G. Joshi, Romil J. Shah
  • Patent number: 9015503
    Abstract: A power control method for a portable electronic device. The portable electronic device comprises a power supply unit and a volatile memory for storing data when the power supply unit supplies power thereto. First, the portable electronic device is set to enter a deep sleep mode. Then, data accessed from the volatile memory is transferred to a non-volatile memory. Finally, except for maintaining sufficient power to restore the device, the power supply unit is turned off.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: April 21, 2015
    Assignee: HTC Corporation
    Inventors: Chun-Sheng Chao, Ching-Tsung Lai, Chung-An Chien
  • Patent number: 9015501
    Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design, for allocating processing functions between a primary processor and a secondary processor is disclosed. A primary processor is provided that performs routine processing duties, including execution of application program code, while the secondary processor is in a sleep state. When the load on the primary processor is deemed to be excessive, the secondary processor is awakened from a sleep state and assigned to perform processing functions that would otherwise need to be performed by the primary processor. If temperatures in the system rise above a threshold, the secondary processor is returned to the sleep state.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Timothy W. Gee, Mark A. Rinaldi
  • Patent number: 9009520
    Abstract: A slew rate controller for a computing system includes a slew rate control module, the slew rate control module further comprising a plurality of sampling modules, each sampling module corresponding to one of a plurality of phase signal inputs, wherein each sampling module receives an input signal, a reference voltage, and the sampling module's respective phase signal input, and wherein each sampling module generates a respective sample of a relationship between the input signal and the reference voltage during a time period indicated by the sampling module's respective phase signal input; and a finite state machine configured to output a slew rate control signal to control a slew rate of the input signal based on the plurality of samples from the sampling modules.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Marcel A. Kossel, Daihyun Lim, Pradeep Thiagarajan
  • Patent number: 9009499
    Abstract: A system for managing energy efficiency and control mechanisms in a network having a virtual machine includes a virtual machine power manager (VMPM) coupled to a virtual machine manager (VMM) and a network component. The VMPM is configured to receive power information from the network component, analyze the power information, generate configuration instructions based on the analyzing and send the configuration instructions to the VMM.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: April 14, 2015
    Assignee: Broadcom Corporation
    Inventor: Wael William Diab
  • Patent number: 8984315
    Abstract: The data processing device comprising at least two processing units, each processing unit (CR1, CR2) being alternately in a first operating mode and in a second operating mode, each processing unit switching to its second operating mode at the end of a transient phase (PHT1, PHT2) comprising at least one activation of resources common to these two processing units; at least one of the two units is configured to switch at least once to its second operating mode with a temporal flexibility, and the instant of switching to its second operating mode, of the processing unit or units exhibiting the said flexibility, is adjusted in such a way that the two units are in their second operating mode after the said common resources have been activated once (26) in the course of the two respective transient phases, if this temporal adjustment is compatible with the said temporal flexibility.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: March 17, 2015
    Assignee: ST-Ericsson (France) SAS
    Inventor: Arnaud Rosay
  • Patent number: 8984316
    Abstract: Secure fast platform hibernation and resumption for computing systems. An embodiment of an apparatus includes a processor to operate according to an operating system, the processor to transition the apparatus to a first reduced power state in response to a request, the transition to the first reduced power state including the processor to store context data for the apparatus in a volatile system memory, and logic to transition the apparatus to a second reduced power state, the logic to write the context data from the volatile system memory to a nonvolatile memory for the transition to the second reduced power state, wherein the logic is to implement one or more security measures for the writing of the context data into the nonvolatile memory.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: March 17, 2015
    Assignee: Intel Corporation
    Inventors: Jeff Forristal, Faraz Siddiqi, Lukasz Mielicki, Hao-Chi Wong
  • Patent number: 8984321
    Abstract: A method of reducing jitter in a local clock of a synchronised USB device attached to a USB Hub, the USB Hub having a local clock and repeater circuitry, comprising: observing a USB data stream with the USB Hub, the data stream having a data stream bit rate; the USB Hub decoding a periodic signal structure in the USB data stream; the USB Hub generating an event signal in response to decoding of the periodic signal structure; and the USB Hub locking a frequency of the local clock of the USB Hub to the periodic event signal. The local clock of the USB Hub is adapted to be a clocking source for the repeater circuitry of the USB Hub at substantially an integer multiple of a frequency of the data stream bit rate.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: March 17, 2015
    Assignee: Chronologic Pty, Ltd.
    Inventors: Peter Graham Foster, Alex Kouznetsov
  • Patent number: 8984324
    Abstract: A method whereby the frequency of the clock of an internal bus of a sink of High Definition Multimedia Interface (HDMI) data is reduced, and possibly deep color mode of a sink deactivated, in response to an inability of a source of HDMI data to read extended display identification data (EDID) and/or effect High Definition Content Protection (HDCP) authentication with the sink.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventor: Peter Shintani
  • Patent number: 8977869
    Abstract: While an IC chip is in idle mode with no power being supplied to the IC chip, the IC chip may be operable to detect a signal pulse received by the IC chip using energy associated with the signal pulse. The IC chip may be operable to control a control signal for a power switch using the energy associated with the signal pulse. The power switch may allow power to be provided to the IC chip based on the control signal. The IC chip may comprise a pulse detector, a latch circuit and an ON/OFF logic circuit within the IC chip. While the IC chip is fully powered and communication with a partner chip is finished, the IC chip may be operable to control the control signal to turn off the power switch for powering down the IC chip based on a turn-off signal.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: March 10, 2015
    Assignee: Broadcom Corporation
    Inventors: Jingguang Wang, Derek Tam, Mark Berman, Siavash Fallahi
  • Patent number: 8959367
    Abstract: A system and computer program product allocates energy entitlement to a logical partition (LPAR) executing on a data processing system. An energy entitlement allocation (EEA) utility enables an administrator to specify a minimum and/or maximum energy entitlement and An LPAR priority. When the relevant LPARs utilize the respective minimum energy entitlement based on respective energy consumption, the EEA utility determines whether the LPAR (and other LPARs) has satisfied a respective maximum energy entitlement. When the LPAR has not satisfied its maximum energy entitlement, the EEA utility allocates unused energy entitlement from the data processing system to the LPAR, according to an allocation policy. Additionally, the EEA utility dynamically adjusts a priority level for the LPAR to efficiently control resource allocation, according to the LPAR's energy consumption relative to its energy entitlement.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: February 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alexander Barraclough Brown, Neil Anthony Campbell, Ryan Jason Cocks
  • Patent number: 8954963
    Abstract: A method of controlling a virtual machine of a computer, the computer comprising: a physical machine comprising an I/O adapter having a physical function that creates a virtual function; a virtualization unit that provides computer resources of the physical machine to the virtual machine; and an OS that is executed on the virtual machine, the virtualization unit creating a virtual machine to which the virtual function is assigned, the virtual machine running the OS thereon, the method comprising: a first step of detecting, by the virtualization unit, a state change of the I/O adapter; a second step of identifying, by the virtualization unit, when a state of the I/O adapter becomes a predetermined state, the virtual machine to which the virtual function is assigned; and a third step of notifying, by the virtualization unit, the OS running on the identified virtual machine of the state of the I/O adapter.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: February 10, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Hattori, Yuta Sawa, Keitaro Uehara