Abstract: A system and method for operating an electronic computing device that is capable of invoking a battery saver mode may monitor an amount of power remaining in a battery of the electronic computing device, and generate an alert when the remaining amount of power in the battery available for continued operation of the device is at or below a predetermined threshold. The alert may include a notification of the estimated power remaining and an option to enable the battery saver mode. The alert may include a notification of the estimated power remaining and that battery saver mode has been enabled, and an option to disable the battery saver mode. The alert may include a notification of the estimated power remaining, and an option to customize the parameters of the battery saver mode by adjusting operation of various features and applications of the device.

Abstract: A system includes a control system and a Remote Terminal Unit (RTU). The control system is configured to communicate data with one or more field devices via the RTU. The RTU is configured to transmit received data from the one or more field devices and the control system. The RTU is also configured to activate a power saving mode that selectively provides power to transmit the received data. The RTU is further configured to, while the power saving mode is activated, prevent power from being provided to transmit the received data, and store the received data in a memory of the RTU when the power is not provided to transmit the received data. The RTU is configured to, while the power saving mode is activated, provide power to transmit the received data after storing the received data in the memory of the RTU.

Abstract: Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.

Abstract: Embodiments herein relate to loading boot data. In an embodiment, a device loads boot data from a first portion of a first non-volatile memory to complete a first booting of the device. The first portion of the first non-volatile memory is then released to allow the device to overwrite the first portion. Next, the boot data is written to the first non-volatile memory before the device enters a reduced power state. The written boot data is to be loaded from the first non-volatile memory to complete a second booting of the device, if the second booting is initiated.

Abstract: Examples include techniques to power down output power rails for a storage device. In some examples, energy discharged from output capacitors for output power rails and energy discharged from input capacitors may be used to facilitate power down of power rails for the storage device.

Abstract: A power management circuit that controls a plurality of power circuits for generating supply voltages at least for a processor is disclosed. The circuit includes: a real time clock that generates clock signals with a predetermined frequency; a power-on terminal to which a power-on key is connected, wherein the power-on terminal receives a voltage whose level depends on whether the power-on key is pressed or not; a power-on detecting unit that monitors a voltage at the power-on terminal and asserts a start signal if it is determined using the clock signals that the power-on key is pressed and held for a predetermined time period; and a power management controller that receives a system voltage based on a battery voltage or a DC voltage from a DC power source and, upon the start signal is asserted, starts up the plurality of power circuits in a predetermined sequence using the clock signals.

Abstract: The present disclosure is directed to firmware block dispatch based on fusing. A device may determine firmware blocks to load during initialization of the device based on fuses set in a processing module in the device. A firmware module may comprise at least a nonvolatile (NV) memory including boot code and a firmware information table (FIT). During initialization the boot code may cause the processing module to read fuse information from a fuse module and to determine at least one firmware block to load based on the fuse information. For example, the fuse information may comprise a fuse string and the processing module may compare the fuse string to the FIT table, determine at least one pointer in the FIT table associated with the fuse string and load at least one firmware block based on a location (e.g., offset) in the NV memory identified by the at least one pointer.

Abstract: A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.

Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to micro-architectural energy monitor event-assisted temperature sensing are described. In one embodiment, at least one of a plurality of slices of a computational logic or at least one of a plurality of sub-slices of the computational logic are powered down or powered up based on a comparison of a temperature value, that is determined based on one or more micro-architectural events, and a threshold value. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.

Abstract: A network element (NE) comprising a receiver configured to couple to a cloud network; and a multi-core central processing unit (CPU) coupled to the receiver and configured to receive a first partition configuration from an orchestration element, partition a plurality of processor cores into a plurality of processor core partitions according to the first partition configuration, and initiate a plurality of virtual basic input/output systems (vBIOSs) such that each vBIOS manages a processor core partition.

Abstract: An information processing apparatus includes a first boot unit, a first image display, a second boot unit, a second image display, a memory, and an image processing unit. The first boot unit boots the information processing apparatus. The first image display performs image display while the first boot unit boots the information processing apparatus. The second boot unit boots the information processing apparatus. The second image display performs image display while the second boot unit boots the information processing apparatus. The memory stores image information. The image processing unit performs image processing on the image information. The first image display performs the image display based on the image information stored in the memory. The second image display performs the image display based on the image information image-processed by the image processing unit.

Abstract: An information processing apparatus according to the present embodiment is capable of transiting to a power saving state and retains a status of a resume requesting device before the information processing apparatus transits to the power saving state. When resuming from the power saving state, the information processing apparatus acquires a status of the resume requesting device. The information processing apparatus further determines a device to which power is supplied based on a result of comparison between the status of the resume requesting device retained and the status of the resume requesting device acquired.

Abstract: An information processing apparatus includes: a communication unit that performs communication with a power supply controller controlling supply and shutoff of power supply of a device; an operation receiving unit that receives input of user operation; an instructing unit that instructs the power supply controller via the communication unit to supply or shut off power supply in response to user operation concerning supply or shutoff of power supply of the device; a setting unit that sets power supply specified to be not permitted to shut off in response to user operation to specify the power supply to be not permitted to shut off; and an instruction disabling unit that disables an instruction to shut off power supply by the instructing unit when the power supply set to be not permitted to shut off is a target of the instruction to shut off power supply by the instructing unit.

Abstract: A method utilizes event-driven reoptimization to reallocate one or more logical partitions within a pool of logically-partitioned data processing systems in a logically-partitioned computing environment in response to detection of a system event that is likely to increase or decrease the collective resource demands of logical partitions resident in a logically-partitioned computing environment. The reoptimization may be used to consolidate logical partitions on fewer processor nodes to improve the potential for powering down hardware resources and thereby reduce power consumption.

Abstract: Some embodiments of a processing device include one or more power supply monitors to provide one or more counts representative of one or more operating frequencies of one or more circuit blocks based on a voltage supplied to the circuit block(s). Some embodiments of the processing device also include a system management unit to determine an initial voltage supplied to the circuit block(s) based on a target count and to reduce the voltage supplied to the circuit block(s) from the initial voltage in response to the count(s) generated by the power supply monitor(s) exceeding the target count.

Abstract: A method of optimizing the number of output stages of a switched mode power supply features a dynamically-updated lookup table (LUT) storing historic output stage configuration data per system operating performance point (OPP). Upon entering an OPP, a margin is added to the historic optimal configuration. During operation at the OPP, the current drawn by the load is periodically monitored, and the number of output stages is dynamically adjusted, as needed (with low pass filtering to ensure stability). When the system exits the OPP, a running average of the optimal number of output stages for the OPP is updated with the actual number of output stages enabled in this iteration of the OPP. A running average of the deviation, or change in number of output stages enabled, is also maintained. The updated values are written to the LUT, for use in setting the initial output stage configuration the next time the same OPP is invoked.

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Abstract: The present invention provides a method of easily managing two or more OSs. A host OS, a guest OS, and a virtualization module are loaded into a primary physical address area of a main memory. The guest OS is executed in a virtual environment in a primary physical address area. A memory image of the guest OS loaded in the primary physical address area is copied to a secondary physical address area. The right of access to a processor is transferred to the guest OS copied in the secondary physical address area to execute the guest OS in a physical environment.