Abstract: A mechanism is described for facilitating power extension service at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes calculating potential power saving by one or more of a plurality of power-saving techniques supported by a computing device. The calculating includes identifying the one or more of the plurality of power-saving techniques that are available for selection and an expected amount of power to be saved with the one or more of the plurality of power saving techniques. The method may further include generating a list identifying the one or more of the plurality of power-saving techniques and relevant information resulting from the calculation, and displaying the list.

Abstract: Serial peripheral interfaces and methods of operating the same are provided. An apparatus can have a serial peripheral interface (SPI) including a first command state machine (CSM), and a second CSM.

Abstract: Provided is a method and apparatus for identifying a type of an external device connected to an interface connector in an electronic device. The electronic device may measure a voltage of power that is input to a power supply terminal of the interface connector that includes the power supply terminal and is configured to connect with an external device. The electronic device may identify a type of the external device connected to the interface connector based on the voltage of the input power. In addition, other embodiments are also possible.

Abstract: It is determined that a current node power consumption for a node is greater than a node power cap that defines a limit of power consumption for the node. Responsive to the current node power consumption being greater than the node power cap and until the current node power consumption is less than the node power cap, power reduction operations are performed. The power reduction operations comprise determining a power management zone of a plurality of power management zones having a lowest priority among the power management zones and having a power cap greater than a minimum power cap for the power management zone. The power reduction operations further comprise setting the power cap for the power management zone to a value less than a prior value assigned as the power cap for the power management zone.

Abstract: Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

Abstract: In one embodiment, an electronic device comprises an oscillator configured to generate an oscillator signal, and a timing circuit configured to generate a count value based on the oscillator signal, to compare the count value with a first compare value, to determine a first expiry event upon the count value matching the first compare value, and to generate a first wakeup signal in response to the first expiry event. The electronic device also comprises a battery pass circuit configured to receive the first wakeup signal, and to couple a power source to a main device in response to the first wakeup signal to power on the main device. The electronic device further comprises a state sequencing circuit configured to store a state of the main device, and an interface circuit configured to communicate the stored state to the main device.

Abstract: It is determined that a current node power consumption for a node is greater than a node power cap that defines a limit of power consumption for the node. Responsive to the current node power consumption being greater than the node power cap and until the current node power consumption is less than the node power cap, power reduction operations are performed. The power reduction operations comprise determining a power management zone of a plurality of power management zones having a lowest priority among the power management zones and having a power cap greater than a minimum power cap for the power management zone. The power reduction operations further comprise setting the power cap for the power management zone to a value less than a prior value assigned as the power cap for the power management zone.

Abstract: There are provided n (n is an integer greater than or equal to 2) physical layer control units which communicate with another apparatus connected to a device itself and control a physical layer, a logical layer control unit which controls a logical layer in communication with the other apparatus, and a control unit which controls the logical layer control unit from a power-supply ON state to a standby state in accordance with a standby instruction for the device itself, wherein one physical layer control unit of the n physical layer control units generates a clock using a connected resonator and the other physical layer control units receive the clock generated by the physical layer control unit to which the resonator is connected.

Abstract: An information device has a storage medium storing information items which includes a first program provided on a first partition, a second program and data provided on a second partition to restore the first program on the first partition to a predetermined state, a boot block which causes system activation from one of the first partition and the second partition, and an active-partition switching program which indicates, to the boot block, one of the first and second partitions. An input/output system activates the active-partition switching program when a specific operation is performed. The active-partition switching program indicates to the boot block that system activation is to be executed from the second partition.

Abstract: A software layout system is described herein that speeds up computer system boot time and/or application initialization time by moving constant data and executable code into byte-addressable, persistent random access memory (BPRAM). The system determines which components and aspects of the operating system or application change infrequently. From this information, the system builds a high performance BPRAM cache to provide faster access to these frequently used components, including the kernel. The result is that kernel or application code and data structures have a high performance access and execution time with regard to memory fetches. Thus, the software layout system provides a faster way to prepare operating systems and applications for normal operation and reduces the time spent on initialization.

Abstract: File sharing circuit and computer using the same are provided. The computer includes a computer host and a file sharing circuit. The computer host includes a first storage device, a first system control chip, a control unit, and a power integrated circuit. The file sharing circuit includes a second system control chip and a first bus switch. When the second system control chip performs a file sharing procedure, the power integrated circuit powers the first storage device, the second system control chip, and the first bus switch, and the control unit switches the first bus switch to a first state so that the second system control chip accesses the first storage device. When the second system control chip does not perform the file sharing procedure, the control unit switches the first bus switch to a second state so that the first system control chip accesses the first storage device.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A power distribution system includes a manager provided on a network controller and an agent provided on a line module. The manager is operable to receive a configuration for a port on the line module. A connection to the port is then detected by the agent and communicated to the manager. At least one of the manager and the agent determines that the connection is for a powered device that is operable to receive power and data through the port. The manager then classifies the powered device. If the manager determines that the classification of the powered device corresponds to the configuration of the port, the manager provides power to the powered device through the port according to an allocation for the powered device from a global power budget.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A computer-implemented method, computer program product, and computer system for identifying power line segments and power line redundancies in a datacenter are provided. The computer-implemented method for identifying power line segments and power line redundancies in a datacenter include; transmitting a data packet from equipment compilers to a host program, where the data packet includes unique datacenter equipment identifiers, the datacenter equipment includes IT equipment and a power source; identifying one or more power line segments from the power source to the IT equipment; and determining an existence of a power line redundancy between the power source and the IT equipment.

Abstract: A controller and a method for power sequencing a computer. The controller may be configured to provide to a south bridge, before the south bridge has completed power management resets, a real time clock signal at a first frequency, and provide to the south bridge, after the south bridge has completed power management resets, a real time clock signal at a second frequency.

Abstract: A mechanism is described for facilitating power extension service at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes calculating potential power saving by one or more of a plurality of power-saving techniques supported by a computing device. The calculating includes identifying the one or more of the plurality of power-saving techniques that are available for selection and an expected amount of power to be saved with the one or more of the plurality of power saving techniques. The method may further include generating a list identifying the one or more of the plurality of power-saving techniques and relevant information resulting from the calculation, and displaying the list.

Abstract: According to an embodiment, an information processing device includes a data obtaining unit and a data storage controller. The data obtaining unit is configured to obtain data measured by a sensor. The data storage controller is configured to store the data obtained by the data obtaining unit in a first memory of volatile nature when a sampling interval indicating an interval at which the data obtaining unit obtains the data is equal to or smaller than a threshold value. The data storage controller is configured to store the data obtained by the data obtaining unit and the data stored in the first memory in a second memory of nonvolatile nature when the sampling interval exceeds the threshold value.

Abstract: Methods and apparatus relating to rotational graphics sub-slice and Execution Unit (EU) power down to improve power performance efficiency are described. In one embodiment, power-gating is rotated amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic. The computational logic includes the plurality of slices and each of the plurality of slices includes a plurality of sub-slices to perform one or more computations. Other embodiments are also disclosed and claimed.

Abstract: A Power-over-Ethernet (PoE) switch selectively controls the supply of power to the PoE output ports on a user-specific basis, based on a network port authentication protocol. The PoE switch includes an accounting information unit storing power usage information on a per-user basis. The PoE switch uses a protocol such as the 802.1x network port authentication protocol.