Abstract: Methods and apparatus for managing sideband segments in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF includes a plurality of segments that may be reset or powered down independently after power management logic determines that in progress messages have been handled and future messages to the segment being reset or powered down will be blocked. Other embodiments are also disclosed.

Abstract: The image forming apparatus includes a first response unit and a second response unit. The first response unit transmits a response including information corresponding to a request in response to a request from a management, via a network. The second response unit includes a storage unit and a control unit. The storage unit stores an item name of the information and an item value corresponding to the item name. The control unit controls so as to restrict power supply to the first response unit and transfers to a second mode in which the second response unit transmits the response in place of the first response unit, when a condition for transferring from the preliminarily set first mode to the second mode is satisfied and an item value corresponding to the stored item name is stored in the storage unit.

Abstract: Systems and methods according to one or more embodiments are provided for detecting or recognizing a user and intelligently altering or adjusting user device settings appropriate for the detected user. In an embodiment, a method comprises detecting, electronically by a processor, a first user interacting with a user device via a user input interface of the user device; determining, electronically by the processor, one or more characteristics associated with a primary user of the user device; determining, electronically by the processor, the first user is not the primary user based at least in part on comparing interactions of the first user with the user device and the one or more characteristics associated with the primary user of the user device; and altering one or more settings of the user device.

Abstract: An embedded controller for power-saving and a method thereof are provided. The embedded controller is used for executing a plurality of tasks and includes a timer module and a control unit. The timer module includes a plurality of timers, and each of timers is corresponding to one of the tasks respectively. The control unit is coupled to the timer module and respectively sets a wake-up period according to each task. When the wake-up period of each timer is expired, each timer respectively generates a wake-up signal to the control unit. The control unit controls the embedded controller to transfer to an active model from an idle model according to the wake-up signals respectively. After executing the tasks corresponding to the wake-up signals respectively, the control unit controls the embedded controller to transfer to the idle model from the active model.

Abstract: The described embodiments include a computing device with an entity (a processor, a processor core, etc.) and a controller. In these embodiments, the controller, using an idle duration history, predicts a duration of a next idle period for the entity. Based on the predicted duration of the next idle period, the controller configures the entity to operate in a corresponding idle state.

Abstract: A data processing system includes a boot read only memory (ROM) configured to store boot code; one time programmable (OTP) storage circuitry configured to store patch instructions; a random access memory (RAM); and a processor coupled to the boot ROM, the OTP storage circuitry, and the RAM. The processor is configured to: in response to a reset of the data processing system, copy one or more patch instructions from the OTP storage circuitry into the RAM, and during execution of the boot code, execute a patch instruction from the RAM in place of a boot instruction of the boot code.

Abstract: In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS RAS services for one or more hardware components, regardless of a particular platform hardware configuration, as long as the platform hardware and OS are in conformance with the PPM interface.

Abstract: A start-up architecture of a redundant power supply system is provided. The redundant power supply system is electrically connected to a load, and includes N+M power supplies, where N?1 and M?1. The start-up architecture includes a power integration backboard electrically connected to the power supplies, and a mode switching member. The power integration backboard includes an activation circuit, and has a synchronous booting mode in which the power supplies are simultaneously activated and a sequential booting mode in which the power supplies are sequentially activated. The mode switching member is electrically connected to the activation circuit, and receives a manual switching of a user to output a synchronous booting signal that controls the power integration backboard to enter the synchronous booting mode and to output a sequential booting signal that controls the power integration backboard to enter the sequential booting mode.

Abstract: An aspect includes a method of interface clock frequency switching control that includes determining a first clock delay adjustment of a clock signal for an interface at a first clock frequency. A controller determines a second clock delay adjustment for the interface operated at a second clock frequency. The controller computes an insertion delay between the clock signal and a data signal of the interface based on the first clock delay adjustment and frequency and the second clock delay adjustment and frequency. The controller also computes a third clock delay adjustment to operate the interface at a third clock frequency based on the insertion delay and a relative difference between the third clock frequency and the second clock frequency. The clock signal is adjusted based on the third clock delay adjustment to align timing of the clock signal with the data signal at the third clock frequency.

Abstract: An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.

Abstract: An appliance network connectivity apparatus includes a voltage sensor that generates a signal at an output that is proportional to a voltage provided to the appliance. A current sensor generates a signal at an output that is proportional to a current flowing through the appliance. A processor determines the electrical characteristics of power consumed by the appliance and executes web server software for communicating data through a network. A relay controls power from the power source to the appliance. A memory stores the electrical characteristics. A network interface provides the electrical characteristics to the network.

Abstract: In a pre-operating system environment on a device prior to loading and running an operating system on the device, a policy identifying configuration settings for the operating system is obtained. The operating system itself is prevented from changing this policy, but the policy can be changed under certain circumstances by components of the pre-operating system environment. The policy is compared to configuration values used by the operating system, and the operating system is allowed to boot with the configuration values if the configuration values satisfy the policy. However, if the configuration values do not satisfy the policy, then a responsive action is taken.

Abstract: Example embodiments of core voltage margining apparatus include a plurality of voltage offset blocks disposed on a multi-core processor with each voltage offset block having a voltage input coupled to receive a supply voltage level, a control input coupled to receive an offset code, and a voltage output coupled to a respective core processor in the multi-core processor, with each voltage offset block configured to offset the supply voltage level by an voltage offset value programmed by an offset code received at the control input of the voltage offset block and a voltage offset register having a like plurality of control outputs each coupled to a corresponding control input of a voltage offset block, where the voltage output register is configured to hold an offset code for each voltage offset block and to provide the offset code, programming the voltage level of a selected voltage offset block, at the control output port coupled to the selected voltage offset block.

Abstract: Apparatus and method for supplying electrical power to a device. A system on chip (SOC) integrated circuit includes a first region having a processing core and a second region characterized as an always on domain (AOD) power island having a power control block with an energy detector coupled to a host input line. First and second power supply modules respectively supply power to the first and second regions. The second power supply module includes a main switch between the first power supply module and a host input voltage terminal. The power control block opens the main switch to enter a low power mode during which no power is supplied to the first region, and the power control block closes the main switch to resume application of power to the first region responsive to the energy detector detecting electrical energy on the host input line.

Abstract: A reprogramming device is used for reprogramming embedded systems. The reprogramming device comprises a microprocessor, a memory programmed with software to accomplish the reprogramming of distinctly different embedded systems architectures, and one or more hardware devices that facilitate communication over multiple protocols contained in a portable package designed for both one-time and multi-occurrence use scenarios. In some embodiments, the reprogramming device is able to be used to enhance one or more attributes of performance of existing embedded systems through the reconfiguration of internally stored parameters. In some embodiments, the reprogramming device is also to be used to extract and receive information and instruction from existing embedded systems and enable useful presentation of this information. As a result, the reprogramming device is able to be used to adjust and/or monitor the parameters of the on-board diagnostics computer of a vehicle to ensure peak performance and detect errors.

Abstract: A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input.

Abstract: An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.

Abstract: A clock control device and method are provided. The clock control device includes a stable time controller which receives an operational condition and generates an expiration counting value based on the operational condition; a stable time counter which receives the expiration counting value and activates a clock gating enable signal after a count value of the stable time counter is equal to the expiration counting value; a clock gating cell which transmits a clock signal after receiving the clock gating enable signal; and an oscillator which generates an oscillator clock signal and transmits the oscillator clock signal to the clock gating cell and the stable time counter.

Abstract: Systems and methods are disclosed for providing auxiliary reserve current to power a system load of an information handing system using an auxiliary energy storage power source as an energy cache to selectably provide auxiliary reserve current to at least partially supplement the normal operating power supply (e.g., battery pack, AC adapter, AC/DC power source, etc.) of an information handling system during temporary times of increased current need by the system load of the information handling system.

Abstract: Methods, systems, and devices are described for managing power consumption in a modem of a mobile device. A receive power associated with a receiver of the modem may be measured during a scheduled power-up of the modem associated with checking for paging messages. A power consumption metric associated with transmitting a pending wireless data transaction at a transmitter of the modem may then be estimated based on the measured receive power associated with the receiver. A determination of whether to transmit the pending wireless data transaction at a first time may then be made based at least in part on the estimated power consumption metric.