Abstract: A system for controlling energy usage in a server having a processor, where the system includes a memory for storing energy cost information, and a controller for determining a transaction rate for the processor. The controller is also for determining a cumulative of energy expended by the server based on the determined transaction rate for each of a number of available power level states (P-states) for operation of the processor, and for selecting one of the available P-states for operation of the processor based on the determined cumulative energy expended and the stored energy cost information.

Abstract: A time slot of regular time length and capacity is defined in time local to a time zone. The slot is defined by a local time start timestamp and a local time end timestamp. In one aspect, upon determining that the local time end timestamp of the slot overlaps with the transition period, the time slot is prolonged beyond the transition period. The prolonged time slot is correspondingly defined by an international standard time start timestamp and an international standard time end timestamp. The prolonged time slot is generated based on the international standard time start timestamp and the international standard time end timestamp.

Abstract: Various embodiments of methods and systems for adaptive thermal management techniques implemented in a portable computing device (“PCD”) are disclosed. Notably, in many PCDs, temperature thresholds associated with various components in the PCD such as, but not limited to, die junction temperatures, package on package (“PoP”) memory temperatures and the “touch temperature” of the external surfaces of the device itself limits the extent to which the performance capabilities of the PCD can be exploited. It is an advantage of the various embodiments of methods and systems for adaptive thermal management that, when a temperature threshold is violated, the performance of the PCD is sacrificed only as much and for as long as necessary to clear the violation before authorizing the thermally aggressive processing component(s) to return to a maximum operating power.

Abstract: Embodiments of the present invention provide a method that comprises, within a sample window, determining an active time of a central processing unit (CPU) at an operating frequency. If there are any different operating frequencies within the sample window, the method further comprises determining active times of the CPU at the different operating frequencies within the sample window and, based upon the active times for the operating frequencies within the sample window, calculating a millions of instructions per second (MIPS) value for the sample window. The method further comprises performing a comparison of the MIPS value to a threshold value and, based upon the comparison of the MIPS value to the threshold value, setting an operating frequency of the CPU for a next sample window.

Abstract: An embodiment may include circuitry to determine whether to issue at least one credit to at least one sender of at least one packet. The credit(s) may be to grant permission to the at least one sender to issue the at least one packet to at least one receiver of the at least one packet. The determination of whether to issue the credit(s) may be based, at least in part, upon whether a time in which the at least one receiver is in a relatively lower power state prior to issuance of the credit(s) is at least sufficient to provide at least a predetermined amount of reduction in power consumption. The relatively lower power state may be relative to a relatively higher power state of the at least one receiver that prevails at the issuance of the credit(s). Additionally or alternatively, the circuitry may be to receive such credit(s).

Abstract: A processor having a multi-Vt critical path is provided that includes both low-Vt devices and high-Vt devices. If the processor is operating in a high performance mode, the multi-Vt critical path is controlled so as to use the low-Vt devices. Conversely, if the processor is operating in a low power mode, the multi-Vt critical path is controlled so as to use the high-Vt devices. In this fashion, the complication of multiple processing cores is avoided in that a single processor core can operate in both the high performance mode and in the low power mode.

Abstract: In one embodiment, a system includes a power management controller that controls a duty cycle of a processor to manage power. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. Before powering the processor up, the power management control may determine whether or not there is work for the processor to perform. If there is no work to perform, the power management control may delay powering the processor up until there is work to perform, saving additional power. This additional power savings may be tracked, and may serve as a “credit” for the processor when subsequently powered up again.

Abstract: A method and apparatus includes a multi-processor apparatus including a plurality of integrated circuit processors having a shared thermal platform. Each processor has at least one subsystem operable at a plurality of different power settings, at least one internal thermal parameter detector providing power data related to the processor, and a power management unit. The method and apparatus illustratively shares power data from the at least one internal thermal parameter detector of each processor between the power management units of the plurality of processors; compares the shared power data from the plurality of processors to a thermal design power limit for the shared thermal platform; and controls a power setting of the at least one subsystem of the plurality of processors within the shared thermal platform based on the comparison of the shared power data to the thermal design power limit for the shared thermal platform.

Abstract: In an embodiment, a clock distribution circuit includes a global delay locked loop (DLL) configured to receive a global clock input signal (RCLK), a lead/lag input signal and to output a clock signal. The circuit includes a plurality of clock distribution blocks, each clock distribution block configured to receive the output of the global DLL, a lead/lag signal and to output a leaf node clock signal, each clock distribution block further comprises a local DLL. The global DLL is further configured to align one of the leaf node clock signals to a reference clock based on its lead/lag input signal. Each clock distribution block is further configured to align its leaf node clock signal to a reference clock based on its lead/lag signal.

Abstract: Apparatus and method for operating a device in a low power mode. In accordance with some embodiments, the apparatus comprises a memory and a system on chip (SOC) integrated circuit. The SOC has a first region with a processing core and a second region electrically isolated from the first region as an always on domain power island with a power control block. In response to a sleep command, the processing core transfers system data to the memory and the power control block enters a low power mode in which no electrical power is supplied to the first region. In response to a wake up command, power is restored to the first region and the processing core performs a reinitialization operation responsive to status information communicated by the power control block indicative of a state of the system during the low power mode.

Abstract: An exemplary method of synchronizing a master clock and a slave clock comprises transmitting a plurality of packets between a master device and a slave device, calculating a first skew between a first pair of the plurality of packets at the slave device and a second skew between the first pair at the master device, calculating a ratio between the first skew and the second skew, providing a slave clock frequency correction to the slave device, calculating a first packet trip delay using a time that the master device initiates sending a packet to the slave device, a time the master device receives a response from the slave device, a corrected time the slave device receives the packet, and a corrected time the slave device initiates sending the response, calculating a first offset based on the first packet trip delay, and providing the first offset to the slave device.

Abstract: The subject matter of this application is embodied in an apparatus that includes a data processor, and two or more hardware monitors to measure parameters associated with the data processor. The apparatus also features a power supply to provide power to the data processor and the hardware monitors, and a controller to control the power supply to adjust an output voltage level of the power supply according to measurements from the hardware monitors. Different weight values are applied to the hardware monitors under different conditions, and the power supply output voltage level is controlled according to weighted measurements or values derived from the weighted measurements.

Abstract: The present disclosure is generally related to power management in a circuit on a circuit board of a processor. The circuit includes a first power connector coupled to a first power input rail. The circuit includes a second power connector and a second power input rail. The circuit includes a control module. The control module is configured to determine a power specification of the circuit board. The control module is configured to detect a power cable connected to the first control connector. The control module is configured to sense a voltage at the second power connector. The control module is configured to couple the second power input rail with the first power connector or the second power connector in response to the determined power specification of the circuit board and the sensed voltage at the second power connector.

Abstract: In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals.

Abstract: A computer peripheral device incorporates a fuel cell that may be used to supply power to a computer device coupled to the peripheral device. The peripheral device comprises a housing and circuitry within the housing to provide at least one computer peripheral function. A data interface provides for data transfer to and/or from a computer device. A fuel cell power source is incorporated into the peripheral device. A power interface provides power transfer to the computer device when connected thereto. A power controller is configured to supply power from the fuel cell power source to the power interface for supplying said power to said computer device when connected thereto.

Abstract: An exemplary method of maintaining secure time in a computing device is disclosed in which one or more processors implements a Rich Execution Environment (REE), and a separate Trusted Execution Environment (TEE). The TEE maintains a real-time clock (RTC) that provides a RTC time to the REE. A RTC offset is stored in non-volatile memory, with the RTC offset indicating a difference between the RTC time and a protected reference (PR) time. Responsive to a request from the REE to read the RTC time, a current RTC time is returned to the REE. Responsive to a request from the REE to adjust the RTC time, the RTC time and the corresponding RTC offset are adjusted by a same amount, such that the PR time is not altered by the RTC adjustment. An exemplary computing device operable to implement the method is also disclosed.

Abstract: In one embodiment, an apparatus may include a rising edge detector to detect a rising edge in a signal. The apparatus may also include a counter to perform a count to a first value based on an input clock signal. The apparatus may also include an output unit to generate a sleep signal after the first value is reached if the rising edge detector does not detect the rising edge in the signal.

Abstract: A system includes a multi-node chassis including a chassis management module, a plurality of compute nodes, and a physical presence manual actuator for transmitting a physical presence signal to each compute node in response to manual actuation. Each server has a firmware interface, a trusted platform module, and an AND gate. The firmware interface has a general purpose input output pin for providing an enabling signal in response to a user instruction to a firmware interface setup program that communicates with the firmware interface. The AND gate has a first input receiving the enabling signal, a second input receiving the physical presence signal, and an output coupled to the trusted platform module, wherein the AND gate for a selected compute node asserts physical presence to the trusted platform module of the selected compute node in response to receiving both the enabling signal and the physical presence signal.

Abstract: Systems and methods may provide for monitoring a current provided from a voltage regulator to a non-core region of a processor, and asserting a throttle signal to the non-core region of the processor if the current exceeds a supply capability threshold of the voltage regulator. In one example, a specified current supply capability of the non-core region is greater than a current supply capability of the voltage regulator, and the supply capability threshold is less than the specified current supply capability of the non-core region and an over current protection threshold of the non-core region.

Abstract: A method and an apparatus for supporting a hibernation function in a mobile device are provided. The method includes receiving an input at an electronic device, loading, using one or more processors, a snapshot image for the electronic device in response to the input, comparing at least one portion of the snapshot image with data indicating a state of the electronic device, and updating the snapshot image using the data, based at least in part on a determination that the state of the electronic device has been changed.